公开(公告)号：US20230384689A1

公开(公告)日：2023-11-30

申请号：US17880700

申请日：2022-08-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shu-Yen LIU ,  Hui-Fang KUO ,  Chian-Ting HUANG ,  Wei-Cyuan LO ,  Yung-Feng CHENG ,  Chung-Yi CHIU

IPC: G03F7/20

CPC classification number: G03F7/70441

Abstract: An optical proximity correction (OPC) device and method is provided. The OPC device includes an analysis unit, a reverse pattern addition unit, a first OPC unit, a second OPC unit and an output unit. The analysis unit is configured to analyze a defect pattern from a photomask layout. The reverse pattern addition unit is configured to provide a reverse pattern within the defect pattern. The first OPC unit is configured to perform a first OPC procedure on whole of the photomask layout. The second OPC unit is configured to perform a second OPC procedure on the defect pattern of the photomask layout to enhance an exposure tolerance window. The output unit is configured to output the photomask layout which is corrected.

公开(公告)号：US20190228127A1

公开(公告)日：2019-07-25

申请号：US15879788

申请日：2018-01-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsung-Yeh WU ,  Chia-Wei HUANG ,  Yung-Feng CHENG

IPC: G06F17/50 ,  H01L21/033 ,  H01L21/02

CPC classification number: G06F17/5072 ,  H01L21/02019 ,  H01L21/0337

Abstract: A method for generating masks for manufacturing of a semiconductor structure comprises the following steps. A design pattern for features to be formed on a substrate is divided into a first set of patterns and a second set of patterns. The first set of patterns comprises a first pattern corresponding to a first feature, the second set of patterns comprises two second patterns corresponding to two second features, and the first feature will be arranged between the two second features when the features are formed on a substrate. Two assist feature patterns are added into the first set of patterns. The two assist feature patterns are arranged in locations corresponding to the two second features, respectively. A first mask is generated based on the first set of patterns with the assist feature patterns. A second mask is generated based on the second set of patterns.

公开(公告)号：US20190250503A1

公开(公告)日：2019-08-15

申请号：US15892935

申请日：2018-02-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsung-Yeh WU ,  Chia-Wei HUANG ,  Yung-Feng CHENG

IPC: G03F1/70 ,  G06F17/50 ,  G03F7/20 ,  G03F1/36

CPC classification number: G03F1/70 ,  G03F1/36 ,  G03F7/70441 ,  G03F7/705 ,  G06F17/5081 ,  G06F2217/12

Abstract: A method for generating masks for manufacturing of a semiconductor structure includes the following steps. First, a design pattern is provided to a processor. The design pattern includes at least one first pattern and at least two second patterns shorter than the first pattern, wherein two of the second patterns are arranged in a line along an extending direction of the patterns. Then, the second patterns are elongated by the processor such that the two second patterns arranged in the line are separated from each other by a distance equal to a minimum space of the design pattern. The design pattern is divided into a first set of patterns and a second set of patterns by the processor. A first mask is generated by the processor based on the first set of patterns. A second mask is generated by the processor based on the second set of patterns.