公开(公告)号：US20210305377A1

公开(公告)日：2021-09-30

申请号：US16831850

申请日：2020-03-27

Applicant: United Microelectronics Corp.

Inventor： ZHUONA MA ,  Mengkai Zhu ,  Runshun Wang ,  Hua-Kuo Lee

IPC: H01L21/28 ,  H01L21/3213 ,  H01L21/311

Abstract: A method for fabricating a semiconductor device is provided. The method includes providing a substrate, having a cell region and a logic region and including a first conductive layer as a top layer, wherein shallow trench isolation (STI) structures are disposed in the substrate at cell region and the logic region. A first dry etching process is performed to preliminarily etch the first conductive layer and the STI structures at the cell region. A wet etching process is performed over the substrate to etch the STI structures down to a preserved height. A control gate stack is formed on the first conductive layer at the cell region. A second dry etching process is performed on a portion of the first conductive layer to form a floating gate under the control gate stack at the cell region and remove the first conductive layer at the logic region.

公开(公告)号：US20240266393A1

公开(公告)日：2024-08-08

申请号：US18119797

申请日：2023-03-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： CHUNYUAN QI ,  XINGXING CHEN ,  ZHUONA MA ,  HUI LIU

IPC: H01L29/06 ,  H01L21/308 ,  H01L27/12 ,  H01L29/16

CPC classification number: H01L29/0657 ,  H01L21/3086 ,  H01L27/1203 ,  H01L29/1604

Abstract: A metasurface structure includes a substrate having a first region and a second region not overlapping with the first region; a first pillar element within the first region on the substrate; and a second pillar element within the second region on the substrate. The first pillar element has a first sectional profile and the second pillar element has a second sectional profile that is different from the first sectional profile. At least one of the first sectional profile and the second sectional profile is of a non-rectangular shape.