公开(公告)号：US09142641B1

公开(公告)日：2015-09-22

申请号：US14516545

申请日：2014-10-16

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chao-Hung Lin ,  Shih-Hung Tsai ,  Ssu-I Fu ,  Jyh-Shyang Jenq

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/308

CPC classification number: H01L29/6656 ,  H01L21/022 ,  H01L21/3086 ,  H01L21/31051 ,  H01L21/31116 ,  H01L29/66795

Abstract: A method for manufacturing a FinFET includes forming a merging spacer, through a plurality of sidewall pattern-transferring processes, and modifying a first interval between adjacent first mandrels as shorter than twice of thicknesses of a nitride layer, which is formed on the first mandrels and contoured thereto, followed by a first spacer being formed on a sidewall thereof, so that a FinFET composed of a plurality of fin-shaped structures having a non-integral multiple of pitches as well as an integral multiple of pitches can be manufactured.

Abstract translation: 一种用于制造FinFET的方法包括：通过多个侧壁图案转移工艺形成合并间隔物，并且修改相邻的第一心轴之间的第一间隔，其长度小于形成在第一心轴上的氮化物层的厚度的两倍， 然后在其侧壁上形成第一间隔物，从而可以制造由具有非整数倍的间距的多个鳍状结构构成的FinFET以及整数倍的间距。

公开(公告)号：US09916978B2

公开(公告)日：2018-03-13

申请号：US15170958

申请日：2016-06-02

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Wei-Chi Cheng ,  Ssu-I Fu ,  Jyh-Shyang Jenq ,  Chao-Hung Lin

IPC: H01L21/3065 ,  H01L21/02 ,  H01L29/66 ,  H01L21/308 ,  H01L21/306

CPC classification number: H01L21/02636 ,  H01L21/02532 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/6656 ,  H01L29/66818

Abstract: The invention provides a method for fabricating a fin field effect transistor (FinFET), comprising: providing a substrate having a logic region and a large region; forming a plurality of fin structures in the logic region by removing a portion of the substrate in the logic region; forming an oxide layer on the substrate filling in-between the fin structures in the logic region; forming an first epitaxial structure in the large region by removing a portion of the substrate in the large region; exposing a portion of the fin structures and a portion of the epitaxial structure by removing a portion of the oxide layer; and forming a gate electrode on portions of the fin structures.