公开(公告)号：US09142641B1

公开(公告)日：2015-09-22

申请号：US14516545

申请日：2014-10-16

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chao-Hung Lin ,  Shih-Hung Tsai ,  Ssu-I Fu ,  Jyh-Shyang Jenq

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/308

CPC classification number: H01L29/6656 ,  H01L21/022 ,  H01L21/3086 ,  H01L21/31051 ,  H01L21/31116 ,  H01L29/66795

Abstract: A method for manufacturing a FinFET includes forming a merging spacer, through a plurality of sidewall pattern-transferring processes, and modifying a first interval between adjacent first mandrels as shorter than twice of thicknesses of a nitride layer, which is formed on the first mandrels and contoured thereto, followed by a first spacer being formed on a sidewall thereof, so that a FinFET composed of a plurality of fin-shaped structures having a non-integral multiple of pitches as well as an integral multiple of pitches can be manufactured.

Abstract translation: 一种用于制造FinFET的方法包括：通过多个侧壁图案转移工艺形成合并间隔物，并且修改相邻的第一心轴之间的第一间隔，其长度小于形成在第一心轴上的氮化物层的厚度的两倍， 然后在其侧壁上形成第一间隔物，从而可以制造由具有非整数倍的间距的多个鳍状结构构成的FinFET以及整数倍的间距。

公开(公告)号：US09916978B2

公开(公告)日：2018-03-13

申请号：US15170958

申请日：2016-06-02

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Wei-Chi Cheng ,  Ssu-I Fu ,  Jyh-Shyang Jenq ,  Chao-Hung Lin

IPC: H01L21/3065 ,  H01L21/02 ,  H01L29/66 ,  H01L21/308 ,  H01L21/306

CPC classification number: H01L21/02636 ,  H01L21/02532 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/6656 ,  H01L29/66818

Abstract: The invention provides a method for fabricating a fin field effect transistor (FinFET), comprising: providing a substrate having a logic region and a large region; forming a plurality of fin structures in the logic region by removing a portion of the substrate in the logic region; forming an oxide layer on the substrate filling in-between the fin structures in the logic region; forming an first epitaxial structure in the large region by removing a portion of the substrate in the large region; exposing a portion of the fin structures and a portion of the epitaxial structure by removing a portion of the oxide layer; and forming a gate electrode on portions of the fin structures.

公开(公告)号：US09362382B1

公开(公告)日：2016-06-07

申请号：US14542685

申请日：2014-11-17

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Yu-Hsiang Hung ,  Yen-Liang Wu ,  Ssu-I Fu ,  Chih-Kai Hsu ,  Jyh-Shyang Jenq

IPC: H01L21/311 ,  H01L21/02 ,  H01L29/66 ,  H01L21/033 ,  H01L21/266

CPC classification number: H01L29/66492 ,  H01L21/0214 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/266 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/66795

Abstract: A method for forming a semiconductor device, includes steps of: providing a substrate; forming a first seal layer over the substrate; forming a second seal layer atop the first seal layer; forming a patterned photoresist layer on the second seal layer; implanting a dopant into the substrate by using the patterned photoresist layer as a mask; executing a first removing process to remove the patterned photoresist layer, wherein the first seal layer has a higher etch rate than that of the second seal layer in the first removing process; and removing the second seal layer after removing the patterned photoresist layer.

Abstract translation: 一种形成半导体器件的方法，包括以下步骤：提供衬底; 在所述基底上形成第一密封层; 在所述第一密封层的顶部形成第二密封层; 在所述第二密封层上形成图案化的光致抗蚀剂层; 通过使用图案化的光致抗蚀剂层作为掩模将掺杂剂注入到衬底中; 执行第一去除过程以去除图案化的光致抗蚀剂层，其中在第一去除过程中，第一密封层具有比第二密封层的蚀刻速率更高的蚀刻速率; 以及在去除图案化的光致抗蚀剂层之后去除第二密封层。

公开(公告)号：US09634125B2

公开(公告)日：2017-04-25

申请号：US15046467

申请日：2016-02-18

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Yen-Liang Wu ,  Chung-Fu Chang ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Wen-Jiun Shen ,  Man-Ling Lu ,  Chia-Jong Liu ,  Yi-Wei Chen

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/66795 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/6656 ,  H01L29/785

Abstract: A field effect transistor (FinFET) device includes a substrate, a fin structure, a shallow trench isolation and a gate structure. The fin structure is formed on a surface of the substrate and includes a base fin structure and an epitaxial fin structure formed on the base fin structure. The shallow trench isolation structure is formed on the surface of the substrate and includes a peripheral zone and a concave zone. The peripheral zone physically contacts with the fin structure. The gate structure is disposed on the epitaxial fin structure perpendicularly. A method of fabricating the aforementioned field effect transistor is also provided.

公开(公告)号：US09123659B1

公开(公告)日：2015-09-01

申请号：US14516554

申请日：2014-10-16

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Ssu-I Fu ,  Shih-Hung Tsai ,  Yu-Hsiang Hung ,  Li-Wei Feng ,  Jyh-Shyang Jenq

IPC: H01L27/088 ,  H01L21/308 ,  H01L29/66 ,  H01L21/762 ,  H01L27/108 ,  H01L21/033

CPC classification number: H01L21/3086 ,  H01L21/0334 ,  H01L21/3083 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/10879 ,  H01L29/66795

Abstract: A method for manufacturing a finFET device is provided. Firstly, a first multiple layer structure and a second multiple layer structure are formed on a substrate in sequence. Then, a first sacrificial pattern is formed on the second multiple layer structure. A first spacer is next formed on a sidewall of the first sacrificial pattern. Subsequently, a portion of the second multiple layer structure is etched so as to form a second sacrificial pattern by using the first spacer as a hard mask. Next, a second spacer is formed on a sidewall of the second sacrificial pattern. After that, the first multiple layer structure is patterned by using the second spacer as a hard mask. Finally, the substrate is etched so as to form at least a first fin structure by using the patterned first multiple layer structure as a hard mask.

Abstract translation: 提供一种制造finFET器件的方法。 首先，依次在基板上形成第一多层结构和第二多层结构。 然后，在第二多层结构上形成第一牺牲图案。 接下来，在第一牺牲图案的侧壁上形成第一间隔物。 随后，蚀刻第二多层结构的一部分，以便通过使用第一间隔物作为硬掩模形成第二牺牲图案。 接下来，在第二牺牲图案的侧壁上形成第二间隔物。 之后，通过使用第二间隔物作为硬掩模来对第一多层结构进行构图。 最后，通过使用图案化的第一多层结构作为硬掩模，蚀刻衬底以形成至少第一鳍结构。