公开(公告)号：US10103248B2

公开(公告)日：2018-10-16

申请号：US15452734

申请日：2017-03-08

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Tai-Ju Chen ,  Yi-Han Ye ,  Te-Chih Chen

IPC: H01L27/148 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L29/40 ,  H01L29/08 ,  H01L29/165 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51

Abstract: A high-voltage FinFET device having LDMOS structure and a method for manufacturing the same are provided. The method includes: providing a substrate with a fin structure to define a first and a second type well regions; forming a trench in the first-type well region to separate the fin structure into a first part and a second part; forming a STI structure in the trench; forming a first and a second polycrystalline silicon gate stack structures at the fin structure; forming discontinuous openings on the exposed fin structure and growing an epitaxial material layer in the openings; doping the epitaxial material layer to form a drain and a source doped layers in the first and second parts respectively; and performing a RMG process to replace the first and second polycrystalline silicon gate stack structures with a first and second metal gate stack structures respectively.

公开(公告)号：US09640663B2

公开(公告)日：2017-05-02

申请号：US14583771

申请日：2014-12-29

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Tai-Ju Chen ,  Yi-Han Ye ,  Te-Chih Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L29/40 ,  H01L29/08 ,  H01L29/06 ,  H01L29/165

CPC classification number: H01L29/66704 ,  H01L21/02532 ,  H01L21/28035 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/165 ,  H01L29/407 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/7851

Abstract: A high-voltage FinFET device having LDMOS structure and a method for manufacturing the same are provided. The high-voltage FinFET device includes: at least one fin structure, a working gate, a shallow trench isolation structure, and a first dummy gate. The fin structure includes a first-type well region and a second-type well region adjacent to the first-type well region, and further includes a first part and a second part. A trench is disposed between the first part and the second part and disposed in the first-type well region. A drain doped layer is disposed on the first part which is disposed in the first-type well region, and a source doped layer is disposed on the second part which is disposed in the second-type well region. The working gate is disposed on the fin structure which is disposed in the first-type well region and in the second-type well region.