公开(公告)号：US20160141386A1

公开(公告)日：2016-05-19

申请号：US14542685

申请日：2014-11-17

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： YU-HSIANG HUNG ,  YEN-LIANG WU ,  SSU-I FU ,  CHIH-KAI HSU ,  JYH-SHYANG JENQ

IPC: H01L29/66 ,  H01L21/266 ,  H01L21/033 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L29/66492 ,  H01L21/0214 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/266 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/66795

Abstract: A method for forming a semiconductor device, includes steps of: providing a substrate; forming a first seal layer over the substrate; forming a second seal layer atop the first seal layer; forming a patterned photoresist layer on the second seal layer; implanting a dopant into the substrate by using the patterned photoresist layer as a mask; executing a first removing process to remove the patterned photoresist layer, wherein the first seal layer has a higher etch rate than that of the second seal layer in the first removing process; and removing the second seal layer after removing the patterned photoresist layer.

Abstract translation: 一种形成半导体器件的方法，包括以下步骤：提供衬底; 在所述基底上形成第一密封层; 在所述第一密封层的顶部形成第二密封层; 在所述第二密封层上形成图案化的光致抗蚀剂层; 通过使用图案化的光致抗蚀剂层作为掩模将掺杂剂注入到衬底中; 执行第一去除过程以去除图案化的光致抗蚀剂层，其中在第一去除过程中，第一密封层具有比第二密封层的蚀刻速率更高的蚀刻速率; 以及在去除图案化的光致抗蚀剂层之后去除第二密封层。

公开(公告)号：US20170352541A1

公开(公告)日：2017-12-07

申请号：US15170958

申请日：2016-06-02

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： CHIH-KAI HSU ,  YU-HSIANG HUNG ,  WEI-CHI CHENG ,  SSU-I FU ,  JYH-SHYANG JENQ ,  CHAO-HUNG LIN

IPC: H01L21/02 ,  H01L21/308 ,  H01L21/306 ,  H01L29/66 ,  H01L21/3065

CPC classification number: H01L21/02636 ,  H01L21/02532 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/6656 ,  H01L29/66818

Abstract: The invention provides a method for fabricating a fin field effect transistor (FinFET), comprising: providing a substrate having a logic region and a large region; forming a plurality of fin structures in the logic region by removing a portion of the substrate in the logic region; forming an oxide layer on the substrate filling in-between the fin structures in the logic region; forming an first epitaxial structure in the large region by removing a portion of the substrate in the large region; exposing a portion of the fin structures and a portion of the epitaxial structure by removing a portion of the oxide layer; and forming a gate electrode on portions of the fin structures.