公开(公告)号：US12040393B2

公开(公告)日：2024-07-16

申请号：US18075433

申请日：2022-12-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Wen Su ,  Ming-Hua Chang ,  Shui-Yen Lu

IPC: H01L29/778 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7787

Abstract: A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, ridges extending along a first direction on the buffer layer, gaps extending along the first direction between the ridges, a p-type semiconductor layer extending along a second direction on the ridges and inserted into the gaps, and a source electrode and a drain electrode adjacent to two sides of the p-type semiconductor layer. Preferably, the source electrode and the drain electrode are extending along the second direction and directly on top of the ridges.

公开(公告)号：US20190214480A1

公开(公告)日：2019-07-11

申请号：US16357333

申请日：2019-03-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Chien Hsieh ,  En-Chiuan Liou ,  Chih-Wei Yang ,  Yu-Cheng Tung ,  Po-Wen Su

IPC: H01L29/66 ,  H01L21/266 ,  H01L21/265 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/7851

Abstract: A fabricating method of a semiconductor structure includes the following steps. A gate material layer is formed on a semiconductor substrate. A patterned mask layer is formed on the gate material layer. The pattern mask layer includes at least one opening exposing a part of the gate material layer. An impurity treatment is performed to the gate material layer partially covered by the pattern mask layer for forming at least one doped region in the gate material layer. An etching process is performed to remove the gate material layer including the doped region. A dummy gate may be formed by patterning the gate material layer, and the impurity treatment may be performed after the step of forming the dummy gate. The performance of the etching processes for removing the gate material layer and/or the dummy gate may be enhanced, and the gate material residue issue may be solved accordingly.

公开(公告)号：US09899491B2

公开(公告)日：2018-02-20

申请号：US15182620

申请日：2016-06-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Wen Su ,  Zhen Wu ,  Hsiao-Pang Chou ,  Chiu-Hsien Yeh ,  Shui-Yen Lu ,  Jian-Wei Chen

IPC: H01L29/51 ,  H01L21/82 ,  H01L27/088 ,  H01L29/66 ,  H01L29/40 ,  H01L21/8234 ,  H01L29/423

CPC classification number: H01L29/512 ,  H01L21/82345 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78

Abstract: A semiconductor device and a method of forming the same, the semiconductor device include a substrate, and a first gate structure and a second gate structure disposed on the substrate. The first gate structure includes a barrier layer, a first work function layer, a second work function layer and a conductive layer stacked one over another on the substrate. The second gate structure includes the barrier layer, a portion of the first work function layer and the conductive layer stacked one over another on the substrate, wherein the portion of the first work function layer has a smaller thickness than a thickness of the first work function layer.

公开(公告)号：US20170330952A1

公开(公告)日：2017-11-16

申请号：US15182620

申请日：2016-06-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Wen Su ,  Zhen Wu ,  Hsiao-Pang Chou ,  Chiu-Hsien Yeh ,  Shui-Yen Lu ,  Jian-Wei Chen

IPC: H01L29/51 ,  H01L29/423 ,  H01L29/40 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L29/512 ,  H01L21/82345 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78

Abstract: A semiconductor device and a method of forming the same, the semiconductor device include a substrate, and a first gate structure and a second gate structure disposed on the substrate. The first gate structure includes a barrier layer, a first work function layer, a second work function layer and a conductive layer stacked one over another on the substrate. The second gate structure includes the barrier layer, a portion of the first work function layer and the conductive layer stacked one over another on the substrate, wherein the portion of the first work function layer has a smaller thickness than a thickness of the first work function layer.

公开(公告)号：US11929418B2

公开(公告)日：2024-03-12

申请号：US17524723

申请日：2021-11-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jie-Ning Yang ,  Wen-Tsung Chang ,  Po-Wen Su ,  Kuan-Ying Lai ,  Bo-Yu Su ,  Chun-Mao Chiou ,  Yao-Jhan Wang

IPC: H01L29/423 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/4966 ,  H01L21/76838 ,  H01L21/76897 ,  H01L21/823437 ,  H01L29/41783 ,  H01L29/42376 ,  H01L29/66545

Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.

公开(公告)号：US11881518B2

公开(公告)日：2024-01-23

申请号：US17523946

申请日：2021-11-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jie-Ning Yang ,  Wen-Tsung Chang ,  Po-Wen Su ,  Kuan-Ying Lai ,  Bo-Yu Su ,  Chun-Mao Chiou ,  Yao-Jhan Wang

IPC: H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/417

CPC classification number: H01L29/4966 ,  H01L21/76838 ,  H01L21/76897 ,  H01L21/823437 ,  H01L29/41783 ,  H01L29/42376 ,  H01L29/66545

Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.

公开(公告)号：US20230100904A1

公开(公告)日：2023-03-30

申请号：US18075433

申请日：2022-12-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Wen Su ,  Ming-Hua Chang ,  Shui-Yen Lu

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/06 ,  H01L29/66 ,  H01L29/20

Abstract: A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, ridges extending along a first direction on the buffer layer, gaps extending along the first direction between the ridges, a p-type semiconductor layer extending along a second direction on the ridges and inserted into the gaps, and a source electrode and a drain electrode adjacent to two sides of the p-type semiconductor layer. Preferably, the source electrode and the drain electrode are extending along the second direction and directly on top of the ridges.

公开(公告)号：US11145733B1

公开(公告)日：2021-10-12

申请号：US17033919

申请日：2020-09-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Hung Chen ,  Chih-Kai Hsu ,  Ssu-I Fu ,  Chia-Jung Hsu ,  Chun-Ya Chiu ,  Yu-Hsiang Lin ,  Po-Wen Su ,  Chung-Fu Chang ,  Guang-Yu Lo ,  Chun-Tsen Lu

IPC: H01L29/423 ,  H01L29/40 ,  H01L21/308 ,  H01L29/51 ,  H01L29/66 ,  H01L21/311 ,  H01L21/28 ,  H01L29/78

Abstract: The present invention discloses a method for forming a semiconductor device with a reduced silicon horn structure. After a pad nitride layer is removed from a substrate, a hard mask layer is conformally deposited over the substrate. The hard mask layer is then etched and trimmed to completely remove a portion of the hard mask layer from an active area and a portion of the hard mask layer from an oblique sidewall of a protruding portion of a trench isolation region around the active area. The active area is then etched to form a recessed region. A gate dielectric layer is formed in the recessed region and a gate electrode layer is formed on the gate dielectric layer.

公开(公告)号：US10283616B2

公开(公告)日：2019-05-07

申请号：US15252200

申请日：2016-08-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Chien Hsieh ,  En-Chiuan Liou ,  Chih-Wei Yang ,  Yu-Cheng Tung ,  Po-Wen Su

IPC: H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/266 ,  H01L29/78

Abstract: A fabricating method of a semiconductor structure includes the following steps. A gate material layer is formed on a semiconductor substrate. A patterned mask layer is formed on the gate material layer. The pattern mask layer includes at least one opening exposing a part of the gate material layer. An impurity treatment is performed to the gate material layer partially covered by the pattern mask layer for forming at least one doped region in the gate material layer. An etching process is performed to remove the gate material layer including the doped region. A dummy gate may be formed by patterning the gate material layer, and the impurity treatment may be performed after the step of forming the dummy gate. The performance of the etching processes for removing the gate material layer and/or the dummy gate may be enhanced, and the gate material residue issue may be solved accordingly.

公开(公告)号：US10177245B2

公开(公告)日：2019-01-08

申请号：US15660919

申请日：2017-07-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Wen Su ,  Shui-Yen Lu

IPC: H01L29/66 ,  H01L21/02

Abstract: A method of fabricating a semiconductor device is disclosed. A substrate is provided. A dummy gate stack is formed on the substrate. The dummy gate stack includes a gate dielectric layer and an amorphous silicon dummy gate on the gate dielectric layer. The amorphous silicon dummy gate is transformed into a nano-crystalline silicon dummy gate. A spacer is formed on a sidewall of the nano-crystalline silicon dummy gate. A source/drain region is formed in the substrate on either side of the dummy gate stack.