-
公开(公告)号：US10468417B2
公开(公告)日：2019-11-05
申请号：US15959291
申请日：2018-04-23
Inventor： Chih-Chien Liu , Tzu-Chin Wu , Po-Chun Chen , Chia-Lung Chang
IPC: H01L23/48 , H01L27/108 , H01L21/02 , H01L21/8234
Abstract: A fabricating method of a stop layer includes providing a substrate. The substrate is divided into a memory region and a peripheral circuit region. Two conductive lines are disposed within the peripheral circuit region. Then, an atomic layer deposition is performed to form a silicon nitride layer to cover the conductive lines. Later, after forming the silicon nitride layer, a silicon carbon nitride layer is formed to cover the silicon nitride layer. The silicon carbon nitride layer serves as a stop layer.
-
公开(公告)号：US10249706B1
公开(公告)日：2019-04-02
申请号：US15951185
申请日：2018-04-12
Inventor： Chia-Lung Chang , Wei-Hsin Liu , Po-Chun Chen , Yi-Wei Chen , Han-Yung Tsai , Tzu-Chin Wu , Shih-Fang Tzou
IPC: H01L49/02 , H01L27/108
Abstract: The present invention provides a semiconductor structure comprising a substrate, a cell region defined on the substrate, a plurality of lower electrodes of the capacitor structures located in the cell region, an top support structure, contacting a top region of the lower electrode structure, and at least one middle support structure located between the substrate and the top support structure, contacting a middle region of the lower electrode structure, wherein when viewed in a top view, the top support structure and the middle support structure do not completely overlapped with each other.
-
公开(公告)号：US10079277B2
公开(公告)日：2018-09-18
申请号：US15362771
申请日：2016-11-28
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Tri-Rung Yew , Hung-Chan Lin , Li-Wei Feng , Chien-Ting Ho , Chia-Lung Chang
IPC: H01L21/20 , H01L49/02 , H01L21/311 , H01L21/3205 , H01L27/108
CPC classification number: H01L28/82 , H01L21/31111 , H01L21/31116 , H01L21/31144 , H01L21/32051 , H01L27/10852 , H01L28/87 , H01L28/91
Abstract: A method of fabricating a metal-insulator-metal capacitor includes providing a dielectric layer. The dielectric layer is etched to form a first hole including a first convex profile bulging into the dielectric layer. Subsequently, the dielectric layer is etched to form a second hole including a second convex profile bulging into the dielectric layer. A first metal layer is formed to conformally cover the capacitor trench. An insulating layer is formed to cover the first metal layer. Finally, a second metal layer is formed covering the insulating layer.
-
公开(公告)号：US20180190658A1
公开(公告)日：2018-07-05
申请号：US15859766
申请日：2018-01-02
Inventor： Mei-Ling Chen , Wei-Hsin Liu , Yi-Wei Chen , Chia-Lung Chang , Jui-Min Lee , Ching-Hsiang Chang , Tzu-Chin Wu , Shih-Fang Tzou
IPC: H01L27/108 , H01L21/768 , H01L21/02
CPC classification number: H01L21/76834 , H01L21/02112 , H01L21/02164 , H01L21/0217 , H01L21/0228 , H01L21/02348 , H01L21/76825 , H01L21/823475 , H01L27/10817 , H01L27/10823 , H01L27/10852 , H01L27/10894 , H01L27/10897 , H01L28/87 , H01L28/91
Abstract: The present invention provides a method for fabricating a semiconductor device, comprising at least the steps of: providing a substrate in which a memory region and a peripheral region are defined, the memory region includes a plurality of memory cells, each memory cell includes at least a first transistor and a capacitor, the peripheral region compress a second transistor, a first insulating layer is formed within the memory region and the peripheral region by an atomic layer deposition process, covering the capacitor of the memory cells in the memory region and the second transistor in the peripheral region, and a second insulating layer is formed, overlying the first insulating layer and the peripheral region. Finally, a contact structure is formed within the second insulating layer, and electrically connecting the second transistor.
-
公开(公告)号：US20140094017A1
公开(公告)日：2014-04-03
申请号：US13633104
申请日：2012-10-01
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Wu-Sian Sie , Chun-Wei Hsu , Chia-Lung Chang , Chih-Hsun Lin , Chang-Hung Kung , Yu-Ting Li , Wei-Che Tsao , Yen-Ming Chen , Chun-Hsiung Wang , Chia-Lin Hsu
IPC: H01L21/762
CPC classification number: H01L21/76232 , H01L21/76229
Abstract: A manufacturing method for a shallow trench isolation. First, a substrate is provided, a hard mask layer and a patterned photoresist layer are sequentially formed on the substrate, at least one trench is then formed in the substrate through an etching process, the hard mask layer is removed. Afterwards, a filler is formed at least in the trench and a planarization process is then performed on the filler. Since the planarization process is performed only on the filler, so the dishing phenomenon can effectively be avoided.
Abstract translation: 浅沟槽隔离的制造方法。 首先，提供基板，在基板上依次形成硬掩模层和图案化光致抗蚀剂层，然后通过蚀刻工艺在基板中形成至少一个沟槽，去除硬掩模层。 然后，至少在沟槽中形成填料，然后对填料进行平面化处理。 由于仅在填料上进行平坦化处理，所以可以有效地避免凹陷现象。
-
Patent Agency Ranking
公开(公告)号：US10770464B2
公开(公告)日：2020-09-08
申请号：US15896091
申请日：2018-02-14
Inventor： Chih-Chien Liu , Chia-Lung Chang , Tzu-Chin Wu , Wei-Lun Hsu
IPC: H01L23/532 , H01L27/108
Abstract: A method for fabricating semiconductor device includes the steps of: forming a bit line structure on a substrate; forming a first spacer, a second spacer, and a third spacer around the bit line structure; forming an interlayer dielectric (ILD) layer on the bit line structure; planarizing part of the ILD layer; removing the ILD layer and the second spacer to form a recess between the first spacer and the third spacer; and forming a liner in the recess.
-
公开(公告)号：US10672864B2
公开(公告)日：2020-06-02
申请号：US16297733
申请日：2019-03-11
Inventor： Tzu-Chin Wu , Wei-Hsin Liu , Yi-Wei Chen , Chia-Lung Chang , Jui-Min Lee , Po-Chun Chen , Li-Wei Feng , Ying-Chiao Wang , Wen-Chieh Lu , Chien-Ting Ho , Tsung-Ying Tsai , Kai-Ping Chen
IPC: H01L49/02 , H01L29/94 , H01L27/108
Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.
-
公开(公告)号：US20190221570A1
公开(公告)日：2019-07-18
申请号：US15896091
申请日：2018-02-14
Inventor： Chih-Chien Liu , Chia-Lung Chang , Tzu-Chin Wu , Wei-Lun Hsu
IPC: H01L27/108 , H01L23/532
Abstract: A method for fabricating semiconductor device includes the steps of: forming a bit line structure on a substrate; forming a first spacer, a second spacer, and a third spacer around the bit line structure; forming an interlayer dielectric (ILD) layer on the bit line structure; planarizing part of the ILD layer; removing the ILD layer and the second spacer to form a recess between the first spacer and the third spacer; and forming a liner in the recess.
-
公开(公告)号：US10332888B2
公开(公告)日：2019-06-25
申请号：US15810145
申请日：2017-11-13
Inventor： Chih-Chien Liu , Chia-Lung Chang , Han-Yung Tsai , Tzu-Chin Wu
IPC: H01L21/285 , H01L27/108
Abstract: A method of manufacturing memory devices is provided in the present invention. The method includes the steps of providing a substrate with multiple capacitors, wherein the capacitor includes a lower electrode layer, an insulating layer and an upper electrode layer and a top plate, forming a tungsten layer on the upper electrode, performing a nitriding plasma treatment to the tungsten layer to form a tungsten nitride layer, and forming a pre-metal dielectric layer on the tungsten nitride layer.
-
公开(公告)号：US10312080B2
公开(公告)日：2019-06-04
申请号：US15859750
申请日：2018-01-02
Inventor： Mei-Ling Chen , Wei-Hsin Liu , Yi-Wei Chen , Ching-Hsiang Chang , Jui-Min Lee , Chia-Lung Chang , Tzu-Chin Wu , Shih-Fang Tzou
IPC: H01L21/02
Abstract: The present invention provides a method for forming an amorphous silicon multiple layer structure, the method comprises the flowing steps: first, a substrate material layer is provided, next, a first amorphous silicon layer is formed on the substrate material layer, wherein the first amorphous silicon layer includes a plurality of hydrogen atoms disposed therein, afterwards, an UV curing process is performed to the first amorphous silicon layer, so as to remove the hydrogen atoms from the first amorphous silicon layer, finally, a second amorphous silicon layer is formed on the first amorphous silicon layer.
-
-
-
-
-
-
-
-
-
Search Results
38
records
(took 0.019 seconds)
