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    Transistor structure
    1.
    发明授权
    Transistor structure 有权

    公开(公告)号：US10431655B2

    公开(公告)日：2019-10-01

    申请号：US15924001

    申请日：2018-03-16

    Applicant: United Microelectronics Corp.

    Inventor： Yen-Ming Chen ,  Chiu-Ling Lee ,  Min-Hsuan Tsai ,  Chiu-Te Lee ,  Chih-Chung Wang

    IPC: H01L29/10 ,  H01L29/06 ,  H01L29/78 ,  H01L29/08

    Abstract: A transistor structure including a substrate, a transistor device, a split buried layer, and a second buried layer is provided. The substrate has a device region. The transistor device is located in the device region. The split buried layer is located under the transistor device in the substrate and includes first buried layers separated from each other. The second buried layer is located under the split buried layer in the substrate and connects the first buried layers. The second buried layer and the split buried layer have a first conductive type. The transistor structure may have a higher breakdown voltage.

    Manufacturing method for a shallow trench isolation
    2.
    发明授权
    Manufacturing method for a shallow trench isolation 有权
    浅沟槽隔离的制造方法

    公开(公告)号：US09012300B2

    公开(公告)日：2015-04-21

    申请号：US13633104

    申请日：2012-10-01

    Applicant: United Microelectronics Corp.

    Inventor： Wu-Sian Sie ,  Chun-Wei Hsu ,  Chia-Lung Chang ,  Chih-Hsun Lin ,  Chang-Hung Kung ,  Yu-Ting Li ,  Wei-Che Tsao ,  Yen-Ming Chen ,  Chun-Hsiung Wang ,  Chia-Lin Hsu

    IPC: H01L21/76 ,  H01L21/762

    CPC classification number: H01L21/76232 ,  H01L21/76229

    Abstract: A manufacturing method for a shallow trench isolation. First, a substrate is provided, a hard mask layer and a patterned photoresist layer are sequentially formed on the substrate, at least one trench is then formed in the substrate through an etching process, the hard mask layer is removed. Afterwards, a filler is formed at least in the trench and a planarization process is then performed on the filler. Since the planarization process is performed only on the filler, so the dishing phenomenon can effectively be avoided.

    Abstract translation: 浅沟槽隔离的制造方法。 首先，提供基板，在基板上顺序地形成硬掩模层和图案化的光致抗蚀剂层，然后通过蚀刻工艺在基板中形成至少一个沟槽，去除硬掩模层。 然后，至少在沟槽中形成填料，然后对填料进行平面化处理。 由于仅在填料上进行平坦化处理，所以可以有效地避免凹陷现象。

    METHOD OF FORMING SEMICONDUCTOR STRUCTURE
    4.
    发明申请
    METHOD OF FORMING SEMICONDUCTOR STRUCTURE 审中-公开
    形成半导体结构的方法

    公开(公告)号：US20150079780A1

    公开(公告)日：2015-03-19

    申请号：US14026634

    申请日：2013-09-13

    Applicant: United Microelectronics Corp.

    Inventor： Yl-Liang Liu ,  Wu-Sian Sie ,  Po-Cheng Huang ,  Chih-Hsien Chen ,  I-Lun Hung ,  Yen-Ming Chen ,  Yu-Ting Li ,  Chang-Hung Kung ,  Chun-Hsiung Wang ,  Chia-Lin Hsu

    IPC: H01L29/66

    CPC classification number: H01L29/66545 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/6656 ,  H01L29/78

    Abstract: A method of forming a semiconductor device is disclosed. A gate structure is formed on a substrate. The gate structure includes a dummy gate and a spacer at a sidewall of the dummy gate. A dielectric layer is formed on the substrate outside of the gate structure. A metal hard mask layer is formed to cover tops of the dielectric layer and the spacer and to expose a surface of the gate structure. The dummy gate is removed to form a gate trench. A low-resistivity metal layer is formed on the metal hard mask layer filling in the gate trench. The low-resistivity metal layer outside of the gate trench is removed. The metal hard mask layer is removed.

    Abstract translation: 公开了一种形成半导体器件的方法。 在基板上形成栅极结构。 栅极结构包括在虚拟栅极的侧壁处的伪栅极和间隔物。 在栅极结构外部的基板上形成电介质层。 形成金属硬掩模层以覆盖电介质层和间隔物的顶部并露出栅极结构的表面。 去除伪栅极以形成栅极沟槽。 在填充在栅极沟槽中的金属硬掩模层上形成低电阻率金属层。 除去栅极沟槽外的低电阻率金属层。 去除金属硬掩模层。

    MANUFACTURING METHOD FOR A SHALLOW TRENCH ISOLATION
    8.
    发明申请
    MANUFACTURING METHOD FOR A SHALLOW TRENCH ISOLATION 有权
    用于浅层分离分离的制造方法

    公开(公告)号：US20140094017A1

    公开(公告)日：2014-04-03

    申请号：US13633104

    申请日：2012-10-01

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wu-Sian Sie ,  Chun-Wei Hsu ,  Chia-Lung Chang ,  Chih-Hsun Lin ,  Chang-Hung Kung ,  Yu-Ting Li ,  Wei-Che Tsao ,  Yen-Ming Chen ,  Chun-Hsiung Wang ,  Chia-Lin Hsu

    IPC: H01L21/762

    CPC classification number: H01L21/76232 ,  H01L21/76229

    Abstract: A manufacturing method for a shallow trench isolation. First, a substrate is provided, a hard mask layer and a patterned photoresist layer are sequentially formed on the substrate, at least one trench is then formed in the substrate through an etching process, the hard mask layer is removed. Afterwards, a filler is formed at least in the trench and a planarization process is then performed on the filler. Since the planarization process is performed only on the filler, so the dishing phenomenon can effectively be avoided.

    Abstract translation: 浅沟槽隔离的制造方法。 首先，提供基板，在基板上依次形成硬掩模层和图案化光致抗蚀剂层，然后通过蚀刻工艺在基板中形成至少一个沟槽，去除硬掩模层。 然后，至少在沟槽中形成填料，然后对填料进行平面化处理。 由于仅在填料上进行平坦化处理，所以可以有效地避免凹陷现象。

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