公开(公告)号：US20140131797A1

公开(公告)日：2014-05-15

申请号：US13674146

申请日：2012-11-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Lin Chen ,  Chih-Chien Chang ,  Ke-Feng Lin ,  Chiu-Te Lee ,  Chih-Chung Wang ,  Chiu-Ling Lee

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/41766 ,  H01L29/66681

Abstract: A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate and extending down from a surface of the substrate; a first well having the first conductive type and a second well having the second conductive type both formed in the deep well and extending down from the surface of the substrate, and the second well spaced apart from the first well; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug penetrating into the isolation and reaching the bottom thereof; and a first doping electrode region having the second conductive type, formed within the second well and below the isolation to connect the conductive plug.

Abstract translation: 半导体结构包括具有第一导电类型的衬底; 具有形成在所述基板中并从所述基板的表面向下延伸的第二导电类型的深阱; 具有第一导电类型的第一阱和具有第二导电类型的第二阱都形成在深阱中并且从衬底的表面向下延伸，并且第二阱与第一阱间隔开; 栅电极，形成在所述基板上并且设置在所述第一阱和所述第二阱之间; 从衬底的表面向下延伸并且设置在栅电极和第二阱之间的隔离件; 导电插塞穿透隔离并到达其底部; 以及具有第二导电类型的第一掺杂电极区域，形成在第二阱内并在隔离件下方以连接导电插塞。

公开(公告)号：US09196723B1

公开(公告)日：2015-11-24

申请号：US14564050

申请日：2014-12-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Yu Chen ,  Tseng-Hsun Liu ,  Min-Hsuan Tsai ,  Te-Chang Chiu ,  Chiu-Ling Lee ,  Chiu-Te Lee

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/45

CPC classification number: H01L29/782 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1079 ,  H01L29/45 ,  H01L29/665 ,  H01L29/7816 ,  H01L29/7817 ,  H01L29/7823 ,  H01L29/872

Abstract: The present invention provides a semiconductor device structure which integrates a lateral diffused metal oxide semiconductor (LDMOS) with a Schottky diode, including: a substrate, having a first conductivity type, a gate positioned on the substrate, a drain region formed in the substrate, the drain region having a second conductivity type complementary to the first conductivity type, a source region formed in the substrate, the source region having the second conductivity type, a high-voltage well region formed in the substrate, the high-voltage well region having a first conductivity type; a Schottky diode disposed on the substrate and disposed beside the LDMOS, wherein the semiconductor device structure is an asymmetric structure, and a deep well region disposed in the substrate and having the second conductivity type, wherein the LDMOS and the Schottky diode are all formed within the deep well region.

Abstract translation: 本发明提供了一种将横向扩散金属氧化物半导体（LDMOS）与肖特基二极管集成的半导体器件结构，包括：具有第一导电类型的衬底，位于衬底上的栅极，形成在衬底中的漏极区， 所述漏极区域具有与所述第一导电类型互补的第二导电类型，形成在所述衬底中的源极区域，具有第二导电类型的源极区域，形成在所述衬底中的高压阱区域，所述高压阱区域具有 第一导电类型; 设置在衬底上并设置在LDMOS旁边的肖特基二极管，其中半导体器件结构是不对称结构，以及设置在衬底中并且具有第二导电类型的深阱区，其中LDMOS和肖特基二极管全部形成在 深井区域。

公开(公告)号：US08994103B2

公开(公告)日：2015-03-31

申请号：US13938252

申请日：2013-07-10

Applicant: United Microelectronics Corp.

Inventor： Wei-Lin Chen ,  Tseng-Hsun Liu ,  Kuan-Yu Chen ,  Chiu-Ling Lee ,  Chiu-Te Lee ,  Chih-Chung Wang

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/66704 ,  H01L29/7825

Abstract: A lateral double-diffused metal-oxide-semiconductor transistor device includes a substrate having at least a shallow trench isolation formed therein, an epitaxial layer encompassing the STI in the substrate, a gate, and a drain region and a source region formed in the substrate at respective two sides of the gate. The epitaxial layer, the source region and the drain region include a first conductivity type. The gate includes a first portion formed on the substrate and a second portion extending into the STI.

Abstract translation: 横向双扩散金属氧化物半导体晶体管器件包括其中形成有至少浅沟槽隔离的衬底，包围衬底中的STI的外延层，栅极和漏极区以及形成在衬底中的源极区 在门的相应两侧。 外延层，源极区和漏极区包括第一导电型。 栅极包括形成在基板上的第一部分和延伸到STI中的第二部分。

公开(公告)号：US20190245041A1

公开(公告)日：2019-08-08

申请号：US15924001

申请日：2018-03-16

Applicant: United Microelectronics Corp.

Inventor： Yen-Ming Chen ,  Chiu-Ling Lee ,  Min-Hsuan Tsai ,  Chiu-Te Lee ,  Chih-Chung Wang

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/1079 ,  H01L29/0649 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/7816 ,  H01L29/7835

Abstract: A transistor structure including a substrate, a transistor device, a split buried layer, and a second buried layer is provided. The substrate has a device region. The transistor device is located in the device region. The split buried layer is located under the transistor device in the substrate and includes first buried layers separated from each other. The second buried layer is located under the split buried layer in the substrate and connects the first buried layers. The second buried layer and the split buried layer have a first conductive type. The transistor structure may have a higher breakdown voltage.

公开(公告)号：US08941175B2

公开(公告)日：2015-01-27

申请号：US13918994

申请日：2013-06-17

Applicant: United Microelectronics Corp.

Inventor： Wei-Lin Chen ,  Ke-Feng Lin ,  Chiu-Ling Lee ,  Chiu-Te Lee ,  Chih-Chung Wang ,  Hsuan-Po Liao

IPC: H01L29/06 ,  H01L29/772 ,  H01L27/088 ,  H01L27/092

CPC classification number: H01L29/7816 ,  H01L27/0207 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/4238 ,  H01L29/78

Abstract: A power array with a staggered arrangement for improving on-resistance and safe operating area of a device is provided. Each power array includes two or more rows with a plurality of parallel device units arranged along the row. Each device unit includes a source region, a drain region, and a gate disposed between the source region and the drain region, wherein each drain region is offset from the adjacent drain region of adjacent rows in a row direction.

Abstract translation: 提供具有交错布置的用于改善设备的导通电阻和安全操作区域的功率阵列。 每个功率阵列包括两行或更多行，具有沿行排列的多个并行设备单元。 每个器件单元包括源极区域，漏极区域和设置在源极区域和漏极区域之间的栅极，其中每个漏极区域在相邻行的相邻漏极区域沿行方向偏移。

公开(公告)号：US10431655B2

公开(公告)日：2019-10-01

申请号：US15924001

申请日：2018-03-16

Applicant: United Microelectronics Corp.

Inventor： Yen-Ming Chen ,  Chiu-Ling Lee ,  Min-Hsuan Tsai ,  Chiu-Te Lee ,  Chih-Chung Wang

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/78 ,  H01L29/08

Abstract: A transistor structure including a substrate, a transistor device, a split buried layer, and a second buried layer is provided. The substrate has a device region. The transistor device is located in the device region. The split buried layer is located under the transistor device in the substrate and includes first buried layers separated from each other. The second buried layer is located under the split buried layer in the substrate and connects the first buried layers. The second buried layer and the split buried layer have a first conductive type. The transistor structure may have a higher breakdown voltage.

公开(公告)号：US09224857B2

公开(公告)日：2015-12-29

申请号：US13674146

申请日：2012-11-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Lin Chen ,  Chih-Chien Chang ,  Ke-Feng Lin ,  Chiu-Te Lee ,  Chih-Chung Wang ,  Chiu-Ling Lee

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/08

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/41766 ,  H01L29/66681

Abstract: A semiconductor structure comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate and extending down from a surface of the substrate; a first well having the first conductive type and a second well having the second conductive type both formed in the deep well and extending down from the surface of the substrate, and the second well spaced apart from the first well; a gate electrode formed on the substrate and disposed between the first and second wells; an isolation extending down from the surface of the substrate and disposed between the gate electrode and the second well; a conductive plug penetrating into the isolation and reaching the bottom thereof; and a first doping electrode region having the second conductive type, formed within the second well and below the isolation to connect the conductive plug.

Abstract translation: 半导体结构包括具有第一导电类型的衬底; 具有形成在所述基板中并从所述基板的表面向下延伸的第二导电类型的深阱; 具有第一导电类型的第一阱和具有第二导电类型的第二阱都形成在深阱中并且从衬底的表面向下延伸，并且第二阱与第一阱间隔开; 栅电极，形成在所述基板上并且设置在所述第一阱和所述第二阱之间; 从衬底的表面向下延伸并且设置在栅电极和第二阱之间的隔离件; 导电插塞穿透隔离并到达其底部; 以及具有第二导电类型的第一掺杂电极区域，形成在第二阱内并在隔离件下方以连接导电插塞。

公开(公告)号：US20150014768A1

公开(公告)日：2015-01-15

申请号：US13938252

申请日：2013-07-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Lin Chen ,  Tseng-Hsun Liu ,  Kuan-Yu Chen ,  Chiu-Ling Lee ,  Chiu-Te Lee ,  Chih-Chung Wang

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/66704 ,  H01L29/7825

Abstract: A lateral double-diffused metal-oxide-semiconductor transistor device includes a substrate having at least a shallow trench isolation formed therein, an epitaxial layer encompassing the STI in the substrate, a gate, and a drain region and a source region formed in the substrate at respective two sides of the gate. The epitaxial layer, the source region and the drain region include a first conductivity type. The gate includes a first portion formed on the substrate and a second portion extending into the STI.

Abstract translation: 横向双扩散金属氧化物半导体晶体管器件包括其中形成有至少浅沟槽隔离的衬底，包围衬底中的STI的外延层，栅极和漏极区以及形成在衬底中的源极区 在门的相应两侧。 外延层，源极区和漏极区包括第一导电型。 栅极包括形成在基板上的第一部分和延伸到STI中的第二部分。

公开(公告)号：US20140367789A1

公开(公告)日：2014-12-18

申请号：US13918994

申请日：2013-06-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Lin Chen ,  Ke-Feng Lin ,  Chiu-Ling Lee ,  Chiu-Te Lee ,  Chih-Chung Wang ,  Hsuan-Po Liao

IPC: H01L27/088 ,  H01L27/092

CPC classification number: H01L29/7816 ,  H01L27/0207 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/4238 ,  H01L29/78

Abstract: A power array with a staggered arrangement for improving on-resistance and safe operating area of a device is provided. Each power array includes two or more rows with a plurality of parallel device units arranged along the row. Each device unit includes a source region, a drain region, and a gate disposed between the source region and the drain region, wherein each drain region is offset from the adjacent drain region of adjacent rows in a row direction.

Abstract translation: 提供具有交错布置的用于改善设备的导通电阻和安全操作区域的功率阵列。 每个功率阵列包括两行或更多行，具有沿行排列的多个并行设备单元。 每个器件单元包括源极区域，漏极区域和设置在源极区域和漏极区域之间的栅极，其中每个漏极区域在相邻行的相邻漏极区域沿行方向偏移。