公开(公告)号：US07030517B2

公开(公告)日：2006-04-18

申请号：US09683662

申请日：2002-01-31

申请人： Uwe Hansmann ,  Lothar Merk ,  Dieter E. Staiger ,  Thomas Stober

发明人： Uwe Hansmann ,  Lothar Merk ,  Dieter E. Staiger ,  Thomas Stober

IPC分类号： H02J7/00

CPC分类号： H02J7/0055 ,  Y10T307/615

摘要： A mobile device (power supplying device) includes a mobile device power server (MD PS) for providing power to another mobile device (power receiving device) having no external power supply connection. The (MD PS) may be integrated into the power supplying mobile device or may be provided as a separate portable connector usable as a connection between the power supplying mobile device and an external power supply adapter.

公开(公告)号：US4648042A

公开(公告)日：1987-03-03

申请号：US616637

申请日：1984-06-04

申请人： Dieter E. Staiger

发明人： Dieter E. Staiger

IPC分类号： G06F12/16 ,  G01R31/28 ,  H03K3/78 ,  G06F3/14 ,  G06F15/34

CPC分类号： H03K3/78

摘要： The present invention is directed to a method of and and apparatus for continuously generating desired pulses during assumed successive desired pulse intervals with a very high time resolution by digitally predetermining the time values related to the start of the desired pulse intervals. These time values are divided into coarse and fine time rasters and coarse pulse intervals are generated from the assumed desired pulse intervals. The coarse pulses in the coarse time raster are generated from the desired pulses and each coarse pulse start and coarse pulse end, respectively is associated with a coarse pulse correction value. By adding the coarse pulse interval correction value to the coarse pulse correction value for the start and the end of the coarse pulse, respectively, a sum correction value is obtained and divided into a partial value associated with the fine time raster. The partial value of the sum correction value is used as a control value for a selected time delay for the coarse pulse edge shifted.

摘要翻译： 本发明涉及一种用于通过数字预先确定与期望的脉冲间隔的开始相关的时间值，在具有非常高的时间分辨率的假定的连续期望脉冲间隔期间连续生成期望脉冲的方法和装置。 这些时间值被划分为粗略和精细时间光栅，并且从假设的期望脉冲间隔产生粗略的脉冲间隔。 粗略时间光栅中的粗略脉冲从期望的脉冲产生，并且每个粗略脉冲起始和粗略脉冲结束分别与粗略的脉冲校正值相关联。 通过将粗脉冲间隔校正值分别与粗脉冲的开始和结束的粗略脉冲校正值相加，获得和校正值，并将其分割为与精细时间光栅相关联的部分值。 总和校正值的部分值被用作对于粗略脉冲边缘移位的所选时间延迟的控制值。

公开(公告)号：US08856370B2

公开(公告)日：2014-10-07

申请号：US11722391

申请日：2005-06-18

申请人： Dieter E. Staiger

发明人： Dieter E. Staiger

IPC分类号： G06F15/16 ,  H04L29/08

CPC分类号： H04L67/34 ,  H04L67/12 ,  H04L69/329

摘要： The present invention provides an electronic network with a plurality of processing units that are arranged in sub-networks in a hierarchical and heterogeneous way. The network features a data stream controller that is coupled to any one of the sub-networks and that is adapted to transmit data to any one of the sub-networks. Further, the network has a data transmission port that is coupled to the data stream controller and that provides a high-speed data transmission to the data stream controller. The data stream controller serves to concurrently provide data and in particular flashing data to the various control units in a way that is adapted to the communication protocol and the data transfer rate of each sub-network. The invention therefore provides fast and autonomous flashing of a plurality of processing units, such as electronic control units in a network embedded system such as commonly used in the framework of automotive electronic networks. The data stream controller and its coupling to the various sub-networks provides a non-hierarchical and direct access to any sub-network and/or control unit of a heterogeneous and hierarchical network.

摘要翻译： 本发明提供了一种电子网络，其具有以分层和异构方式布置在子网络中的多个处理单元。 网络具有数据流控制器，该数据流控制器耦合到任何一个子网络，并且适于将数据发送到任何一个子网络。 此外，网络具有耦合到数据流控制器并且向数据流控制器提供高速数据传输的数据传输端口。 数据流控制器用于以适合于每个子网络的通信协议和数据传输速率的方式向各种控制单元同时提供数据，特别是闪烁数据。 因此，本发明提供了诸如在汽车电子网络的框架中通常使用的网络嵌入式系统中的诸如电子控制单元的多个处理单元的快速和自主的闪烁。 数据流控制器及其与各个子网络的耦合提供对异构和分层网络的任何子网络和/或控制单元的非分层和直接访问。

公开(公告)号：US5752065A

公开(公告)日：1998-05-12

申请号：US477207

申请日：1995-06-07

申请人： Dieter E. Staiger

发明人： Dieter E. Staiger

IPC分类号： G06F9/32 ,  G06F9/22 ,  G06F9/26 ,  G06F15/76

CPC分类号： G06F9/223 ,  G06F9/265

摘要： A processing unit (100) with a processor (110) for processing an operation code and a method for processing the operation code in the processing unit (100). The processor (110) comprises an operation code control unit (200) for receiving and processing the operation code in a boolean circuit (230) and generating a logical result thereof, and a next address control unit (210) comprising a multiplexing unit (250) with a plurality of input lines (A-D) selectable by the multiplexing unit (250) by means of the logical result of the boolean circuit (230). The processor (110) is triggerable by a trigger signal (CLOCK) and each operation code is processable by the processor (110) between successive trigger signals (CLOCK). When the trigger signal appears, the processor (110) issues a signal comprising an address of the operation code to be processed to the control memory (129) and/or a user data memory (140). The operation code corresponding to that address is loaded from the control memory (120) to the processor (110) and processed therein. One result of this processing is that the address of the successive operation code, which will be processed when the successive trigger signal appears. This loading and processing of operation code happens continuously in each cycle between successive trigger signals, until the end of program is reached or an interrupt signal is calling a stop routine. Each operation code is processed between successive trigger signals (or within one CLOCK cycle) allowing a predictable timing of a sequence of operation codes so that a real time condition is achievable.

摘要翻译： 一种处理单元（100），具有用于处理操作代码的处理器（110）和用于在处理单元（100）中处理操作代码的方法。 处理器（110）包括一个操作代码控制单元（200），用于在布尔电路（230）中接收和处理操作代码并产生其逻辑结果;以及下一个地址控制单元（210），包括多路复用单元 ），具有通过布尔电路（230）的逻辑结果由多路复用单元（250）选择的多个输入线（AD）。 处理器（110）可由触发信号（CLOCK）触发，并且每个操作代码可由处理器（110）在连续的触发信号（CLOCK）之间处理。 当触发信号出现时，处理器（110）向控制存储器（129）和/或用户数据存储器（140）发出包括要处理的操作代码的地址的信号。 对应于该地址的操作代码从控制存储器（120）加载到处理器（110）并在其中进行处理。 该处理的一个结果是连续的操作码的地址，当连续的触发信号出现时将被处理。 这种操作代码的加载和处理在连续的触发信号之间的每个周期中连续发生，直到程序结束或者中断信号正在调用停止程序。 每个操作代码在相继的触发信号之间（或在一个CLOCK周期内）处理，从而允许操作代码序列的可预测的定时，从而实现实时条件。

公开(公告)号：US5479415A

公开(公告)日：1995-12-26

申请号：US209671

申请日：1994-03-10

申请人： Dieter E. Staiger

发明人： Dieter E. Staiger

IPC分类号： G01R31/3183 ,  G01R31/319 ,  G11C29/56 ,  G06F11/00

CPC分类号： G01R31/31928 ,  G01R31/31922 ,  G11C29/56

摘要： A circuit for generating product-specific digital test signals for testing memories, etc., the test signals comprising a test pulse occurring during a pulse interval and generated from predetermined data and timing signals. A format memory (7-11) stores addressable test signal formats (in the form of digital values denoting the test signals curve unrelated to time) for each data signal. These digital values are read out time parallel to each other and are combined by a flip-flop circuit (7-24) in the order of their occurrence during the pulse interval with timing signals for the respective data signal to form a control signal. The internal signal delay of the flip-flop circuit determining the generation of the test signals is invariably of the same value. This circuit may not only be used for test purposes but also generally for computer control, in particular for addressing main memories and buffers.

摘要翻译： 用于产生用于测试存储器的产品特定数字测试信号的电路等，所述测试信号包括在脉冲间隔期间发生并由预定数据和定时信号产生的测试脉冲。 格式存储器（7-11）存储每个数据信号的可寻址测试信号格式（以表示与时间无关的测试信号曲线的数字值的形式）。 这些数字值被读出时间彼此平行，并且通过触发器电路（7-24）以其在脉冲间隔期间发生的顺序与用于相应数据信号的定时信号组合，以形成控制信号。 确定测试信号的产生的触发器电路的内部信号延迟总是相同的值。 该电路不仅可用于测试目的，还可用于计算机控制，特别是用于寻址主存储器和缓冲器。

公开(公告)号：US06628441B1

公开(公告)日：2003-09-30

申请号：US09380648

申请日：1999-09-07

申请人： Dieter E. Staiger

发明人： Dieter E. Staiger

IPC分类号： H04B1000

CPC分类号： H04B10/803 ,  G02B6/43

摘要： The invention relates to a bi-directional optical data transfer system. The data is transferred by a diffuse light between several electronic components with several transmission links, wherein each transmission link is provided with a covering to prevent the transmission links from interfering with each other.

摘要翻译： 本发明涉及一种双向光学数据传输系统。 数据通过漫射光在具有几个传输链路的几个电子部件之间传送，其中每个传输链路设置有覆盖物以防止传输链路彼此干扰。

公开(公告)号：US06282664B1

公开(公告)日：2001-08-28

申请号：US09007298

申请日：1998-01-14

申请人： Dieter E. Staiger

发明人： Dieter E. Staiger

IPC分类号： G06F126

CPC分类号： G06F1/3265 ,  G06F1/32 ,  G09G2330/021 ,  Y02D10/153 ,  Y10T307/826

摘要： The invention relates to an electronic system, in particular a mobile data capture and data output device in which the electronic system has a processor (1) and at least one i/o unit (8) with a control unit (7), and in which the processor (1) is connected to the control unit (7), and the control unit (7) is connected with at least one i/o unit (8). The electronic system is switched to a standby-mode, in which a control software unit (2), which is connected to the processor (1) and the control unit (7) executes part of the processor work, and the control software unit (2) monitors the time when data input from at least one i/o unit (8) commences. If commencement of data input is registered the steps needed for data capture are initiated and concluded before the data input is terminated.

摘要翻译： 本发明涉及电子系统，特别是移动数据捕获和数据输出设备，其中电子系统具有处理器（1）和至少一个具有控制单元（7）的i / o单元（8），并且 处理器（1）连接到控制单元（7），并且控制单元（7）与至少一个i / o单元（8）连接。 电子系统切换到待机模式，其中连接到处理器（1）和控制单元（7）的控制软件单元（2）执行处理器工作的一部分，以及控制软件单元 2）监视从至少一个i / o单元（8）输入的数据开始的时间。 如果数据输入的开始被注册，数据采集所需的步骤将在数据输入终止之前启动并结束。

公开(公告)号：US5630109A

公开(公告)日：1997-05-13

申请号：US487371

申请日：1995-06-07

申请人： Dieter E. Staiger

发明人： Dieter E. Staiger

IPC分类号： G01R31/3183 ,  G01R31/319 ,  H03K3/64 ,  H03K3/78 ,  G06F1/04

CPC分类号： H03K3/78 ,  G01R31/31922

摘要： A frequency and timing generator is presented with high accuracy and frequency resolution and no switching time between different timing cycles for a wide applicable frequency range, wherein the repetition rate of the timing cycles is not limited by the processing speed of the components. The frequency and timing generator according to the invention is accomplished by an apparatus for parallel processing of a series of timing signals comprising at least one processing unit for processing and calculating time values from timing parameters representing the series of timing signals, an output unit for outputting the series of timing signals, and an input unit for inputting the timing parameters. The sequences of n successive timing parameters to be parallelly processed are distributable by the input unit to n processing units. A first time value from a first one of the timing parameters is calculatable by a first one of the processing units, and a succesive time value is calculatable by a succesive one of the processing units from the corresponding successive timing parameter of the sequence and the calculated time value of the respective preceding timing parameter.

摘要翻译： 频率和定时发生器在宽适用频率范围内以高精度和频率分辨率呈现不同定时周期之间的切换时间，其中定时周期的重复率不受组件的处理速度的限制。 根据本发明的频率和定时发生器由一种用于并行处理一系列定时信号的装置来实现，该装置包括至少一个处理单元，用于从表示一系列定时信号的定时参数处理和计算时间值;输出单元，用于输出 一系列定时信号，以及用于输入定时参数的输入单元。 要并行处理的n个连续定时参数的序列可由输入单元分配到n个处理单元。 来自第一个定时参数的第一时间值可由处理单元中的第一个计算，并且随后的时间值可由来自该序列的相应连续定时参数的处理单元中的一个处理单元计算， 时间值。

公开(公告)号：US20100115120A1

公开(公告)日：2010-05-06

申请号：US11722391

申请日：2005-06-18

申请人： Dieter E. Staiger

发明人： Dieter E. Staiger

IPC分类号： G06F15/16

CPC分类号： H04L67/34 ,  H04L67/12 ,  H04L69/329

摘要： The present invention provides an electronic network with a plurality of processing units that are arranged in sub-networks in a hierarchical and heterogeneous way. The network features a data stream controller that is coupled to any one of the sub-networks and that is adapted to transmit data to any one of the sub-networks. Further, the network has a data transmission port that is coupled to the data stream controller and that provides a high-speed data transmission to the data stream controller. The data stream controller serves to concurrently provide data and in particular flashing data to the various control units in a way that is adapted to the communication protocol and the data transfer rate of each sub-network. The invention therefore provides fast and autonomous flashing of a plurality of processing units, such as electronic control units in a network embedded system such as commonly used in the framework of automotive electronic networks. The data stream controller and its coupling to the various sub-networks provides a non-hierarchical and direct access to any sub-network and/or control unit of a heterogeneous and hierarchical network.

摘要翻译： 本发明提供了一种电子网络，其具有以分层和异构方式布置在子网络中的多个处理单元。 网络具有数据流控制器，该数据流控制器耦合到任何一个子网络，并且适于将数据发送到任何一个子网络。 此外，网络具有耦合到数据流控制器并且向数据流控制器提供高速数据传输的数据传输端口。 数据流控制器用于以适合于每个子网络的通信协议和数据传输速率的方式向各种控制单元同时提供数据，特别是闪烁数据。 因此，本发明提供了诸如在汽车电子网络的框架中通常使用的网络嵌入式系统中的诸如电子控制单元的多个处理单元的快速和自主的闪烁。 数据流控制器及其与各个子网络的耦合提供对异构和分层网络的任何子网络和/或控制单元的非分层和直接访问。

公开(公告)号：US06950312B2

公开(公告)日：2005-09-27

申请号：US10255840

申请日：2002-09-26

申请人： Dieter E. Staiger

发明人： Dieter E. Staiger

IPC分类号： H05K1/18 ,  H05K13/00 ,  H05K5/00

CPC分类号： H05K1/189 ,  Y10T29/49187 ,  Y10T29/4973

摘要： The present invention discloses method for packaging and assembly of electronic units comprising a multi-planar board system in which each single planar board provides electrical contacts and/or signal drive to its successive planar board via a flexible cable forming the only connection between successive planar boards. In its packaged position the planar boards are laid upon one another without affixing them with each other or affixing them with the housing of the electronic unit, wherein the packaging of the planar boards preferably forming a daisy chain. Positioning and adjusting of the planar boards to each other is mainly achieved by the cover element being wrapped around all surfaces of the planar boards during the packaging process, positioning and clamping of the packaging of the planar boards within the housing is mainly achieved by the self-adapting suspension during the assembly process of the electronic unit into the housing. The cover element separating and concurrently adjusting each planar boards to each other has isolating, stabilizing, heat draining, and flexible attributes. The electronic unit is preferably arranged in a screw-less, and scalable housing.

摘要翻译： 本发明公开了一种用于包装和组装电子单元的方法，其包括多平面板系统，其中每个单个平面板通过柔性电缆为连续的平面板提供电触点和/或信号驱动，所述柔性电缆形成连续平面板之间的唯一连接 。 在其封装位置，平面板相互放置而不将它们彼此固定或者将它们固定在电子单元的壳体上，其中平面板的封装优选地形成菊花链。 平面板彼此的定位和调整主要是通过在包装过程中将盖元件缠绕在平面板的所有表面上来实现的，所述平面板在壳体内的包装的定位和夹紧主要由自身 在电子单元组装过程中将其悬挂在壳体内。 分离并同时调整每个平面板的盖元件具有隔离，稳定，排热和灵活的属性。 电子单元优选地布置在无螺丝的可伸缩壳体中。