利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

32 条记录 (耗时 0.075 秒)

    METHODS, SYSTEMS, AND DEVICES FOR ACCURATE SIGNAL TIMING OF POWER COMPONENT EVENTS
    3.
    发明申请
    METHODS, SYSTEMS, AND DEVICES FOR ACCURATE SIGNAL TIMING OF POWER COMPONENT EVENTS 审中-公开

    公开(公告)号：US20190138371A1

    公开(公告)日：2019-05-09

    申请号：US16182519

    申请日：2018-11-06

    申请人： Kesheng Wu ,  Alex Sim ,  Jonathan Wang ,  Seongwook Hwangbo

    发明人： Kesheng Wu ,  Alex Sim ,  Jonathan Wang ,  Seongwook Hwangbo

    IPC分类号： G06F9/54 ,  G06F17/50 ,  G05B23/02

    摘要： Disclosed herein are methods, systems, and devices for system event detection associated with power grid components. Methods include detecting, at a plurality of sensors, emissions from a system event associated with at least one winding of a power component. Methods also include determining, using a processor, a plurality of event parameters based, at least in part, on measurements made by the plurality of sensors, the event parameters identifying arrival times of the emissions at each of the plurality of sensors. Methods further include generating, using the processor, an output identifying an estimate of a position of the system event within the power component, the estimate being generated based, at least in part, on the arrival times identified by the plurality of event parameters.

    ANTIBODY BOUND SYNTHETIC VESICLE CONTAINING MOLECULES FOR DELIVER TO CENTRAL AND PERIPHERAL NERVOUS SYSTEM CELLS
    5.
    发明申请
    ANTIBODY BOUND SYNTHETIC VESICLE CONTAINING MOLECULES FOR DELIVER TO CENTRAL AND PERIPHERAL NERVOUS SYSTEM CELLS 审中-公开
    含有分子转运至中央和外周神经系统细胞的抗体结合合成途径

    公开(公告)号：US20110097392A1

    公开(公告)日：2011-04-28

    申请号：US12988479

    申请日：2009-04-17

    申请人： Kevin Ka-wang Wang ,  Jonathan Wang ,  Jared V. Goodman ,  Stephen Frank Larner

    发明人： Kevin Ka-wang Wang ,  Jonathan Wang ,  Jared V. Goodman ,  Stephen Frank Larner

    IPC分类号： A61K9/127 ,  C12N5/0793 ,  C12N9/99 ,  A61K47/42 ,  A61K9/00 ,  A61K39/395 ,  A61P25/00

    CPC分类号： C07K16/286 ,  A61K9/127 ,  A61K47/6913 ,  A61K49/0043 ,  A61K49/0054 ,  A61K49/0058 ,  A61K49/0084

    摘要： A process is provided of delivering at least one active agent cargo molecule into an neuronal cell whereby a cargo molecule is placed within a synthetic vesicle such as a liposome and a biotinylated protein such as an antibody is bound to the synthetic vesicle to form a protein bound synthetic vesicle whereby the protein recognizes a receptor expressed on the surface of a neuronal cell, and exposing the protein bound synthetic vesicle to the cell until the cargo molecule is delivered into the neuronal cell. Numerous cargo molecules are delivered by the inventive synthetic vesicle including a calpain inhibitor and a caspase inhibitor. The protein illustratively targets a cellular receptor for a ligand such as glutamate, glycine, dopamine, nicotine, muscarine, acetylcholine, or serotonin, and the like.

    摘要翻译： 提供了将至少一种活性剂货物分子递送到神经元细胞中的方法，由此将货物分子置于合成泡囊（例如脂质体）内，并且生物素化蛋白（例如抗体）与合成泡囊结合以形成结合蛋白 合成囊泡，由此蛋白质识别在神经元细胞表面上表达的受体，并将蛋白质结合的合成囊泡暴露于细胞，直到货物分子被递送到神经元细胞中。 许多货物分子由本发明的合成囊泡递送，包括钙蛋白酶抑制剂和胱天蛋白酶抑制剂。 该蛋白质说明性地靶向配体如谷氨酸，甘氨酸，多巴胺，尼古丁，毒蕈碱，乙酰胆碱或血清素等的细胞受体。

    Double burette syringe
    6.
    发明申请
    Double burette syringe 审中-公开
    双重滴定管注射器

    公开(公告)号：US20100010436A1

    公开(公告)日：2010-01-14

    申请号：US12217740

    申请日：2008-07-09

    申请人： Jen Chuan Wang ,  Joan Wang ,  Jonathan Wang

    发明人： Jen Chuan Wang ,  Joan Wang ,  Jonathan Wang

    IPC分类号： A61M31/00

    CPC分类号： B65D81/325

    摘要： The present invention discloses a device, which comprises a double burette syringe, a stopper, a slidable plate for mixing, and a plurality of mixing bars easily detachable from the mixing plate. This invention relates to devices for storing, delivering, and mixing of a two component double burette syringe.

    摘要翻译： 本发明公开了一种装置，其包括双重滴定管注射器，止动件，用于混合的可滑动板，以及容易从混合板拆卸的多个混合杆。 本发明涉及用于存储，输送和混合双组分双重滴定管注射器的装置。

    Methods, systems, and devices for accurate signal timing of power component events
    7.
    发明授权
    Methods, systems, and devices for accurate signal timing of power component events 有权

    公开(公告)号：US10908972B2

    公开(公告)日：2021-02-02

    申请号：US16182519

    申请日：2018-11-06

    申请人： Kesheng Wu ,  Alex Sim ,  Jonathan Wang ,  Seongwook Hwangbo

    发明人： Kesheng Wu ,  Alex Sim ,  Jonathan Wang ,  Seongwook Hwangbo

    IPC分类号： G06F9/54 ,  G05B23/02 ,  G06F30/23

    摘要： Disclosed herein are methods, systems, and devices for system event detection associated with power grid components. Methods include detecting, at a plurality of sensors, emissions from a system event associated with at least one winding of a power component. Methods also include determining, using a processor, a plurality of event parameters based, at least in part, on measurements made by the plurality of sensors, the event parameters identifying arrival times of the emissions at each of the plurality of sensors. Methods further include generating, using the processor, an output identifying an estimate of a position of the system event within the power component, the estimate being generated based, at least in part, on the arrival times identified by the plurality of event parameters.

    Methods and systems to reduce display artifacts when changing display clock rate
    10.
    发明授权
    Methods and systems to reduce display artifacts when changing display clock rate 有权
    改变显示时钟速率时减少显示伪影的方法和系统

    公开(公告)号：US09070198B2

    公开(公告)日：2015-06-30

    申请号：US13485205

    申请日：2012-05-31

    申请人： Collis Quinn Carter ,  Natan Shtutman ,  Jonathan Wang ,  Stephen Ho ,  Nicholas James Chorney

    发明人： Collis Quinn Carter ,  Natan Shtutman ,  Jonathan Wang ,  Stephen Ho ,  Nicholas James Chorney

    IPC分类号： G06T1/20

    CPC分类号： G06T1/20

    摘要： Methods, systems, and computer readable media embodiments for reducing or eliminating display artifacts caused by on-the-fly changing of the display clock are disclosed. According to an embodiment of the present invention, a method includes, changing a rate of a display clock, and adapting a display data processing pipeline clocked by the display clock to prevent a substantial change in a pixel output rate from the display data processing pipeline based upon the changing.

    摘要翻译： 公开了用于减少或消除由显示时钟的飞行改变引起的显示伪像的方法，系统和计算机可读介质实施例。 根据本发明的实施例，一种方法包括：改变显示时钟的速率，以及调整由显示时钟计时的显示数据处理流水线，以防止基于显示数据处理流水线的像素输出速率的实质性变化 在变化中