公开(公告)号：US07061300B2

公开(公告)日：2006-06-13

申请号：US09797204

申请日：2001-02-27

申请人： Valerio Pisati ,  Marco Cazzaniga ,  Alessandro Venca

发明人： Valerio Pisati ,  Marco Cazzaniga ,  Alessandro Venca

IPC分类号： G05F1/10

CPC分类号： G06G7/163 ,  H03D7/1408 ,  H03D7/1433 ,  H03D7/1491 ,  H03D2200/0086

摘要： The invention relates to a low supply voltage analog multiplier which comprises a pair of differential cells, each cell comprising a pair of bipolar transistors with coupled emitters. A first transistor of each cell receives an input signal on its base terminal and has its collector terminal coupled to a first voltage reference through a bias member. Advantageously, the second transistor of each cell is a diode configuration, and the cells are interconnected at a common node corresponding to the base terminals of the second transistors in each pair. This multiplier can be supplied very low voltages and still exhibit a high rate of operation along with reduced harmonic distortion of the output signal, even with input signals of peak-to-peak amplitude above 600 mV.

摘要翻译： 本发明涉及一种低电源模拟乘法器，其包括一对差分单元，每个单元包括一对具有耦合发射极的双极晶体管。 每个单元的第一晶体管在其基极端子上接收输入信号，并且其集电极端子通过偏置构件耦合到第一电压基准。 有利地，每个单元的第二晶体管是二极管配置，并且这些单元在对应于每对中的第二晶体管的基极端子的公共节点处互连。 该乘法器可以提供非常低的电压，并且仍然表现出高的运行速率以及降低的输出信号的谐波失真，即使高峰值幅度高于600 mV的输入信号也是如此。

公开(公告)号：US07024447B2

公开(公告)日：2006-04-04

申请号：US09794303

申请日：2001-02-27

申请人： Valerio Pisati ,  Augusto Rossi ,  Giorgio Betti ,  Marco Cazzaniga

发明人： Valerio Pisati ,  Augusto Rossi ,  Giorgio Betti ,  Marco Cazzaniga

IPC分类号： G06G7/02 ,  G06F17/10

CPC分类号： H03H17/0211 ,  G11B20/10009

摘要： A finite impulse response (FIR) filter for implementing a Hilbert transform is provided. The FIR filter includes a plurality of programmable delay cells connected in cascade between an input terminal of the FIR filter and an output terminal of the FIR filter. Each programmable delay cell has associated therewith a constant filter coefficient and a programmable delay coefficient. The FIR filter is also applicable for processing signals originated by the reading of data from a magnetic storage media which employs perpendicular recording.

摘要翻译： 提供了一种用于实现希尔伯特变换的有限脉冲响应（FIR）滤波器。 FIR滤波器包括在FIR滤波器的输入端子和FIR滤波器的输出端子之间级联连接的多个可编程延迟单元。 每个可编程延迟单元与其相关联，具有恒定的滤波器系数和可编程延迟系数。 FIR滤波器也可用于处理由采用垂直记录的磁存储介质读取数据所产生的信号。

公开(公告)号：US06424172B1

公开(公告)日：2002-07-23

申请号：US09796996

申请日：2001-02-28

申请人： Valerio Pisati ,  Salvatore Portaluri ,  Marco Cazzaniga ,  Rinaldo Castello

发明人： Valerio Pisati ,  Salvatore Portaluri ,  Marco Cazzaniga ,  Rinaldo Castello

IPC分类号： H03K19082

CPC分类号： H03H11/0422

摘要： This invention relates to a circuit structure of the feedforward type with programmable zeroes, particularly for synthesizing time-continual filters. This structure comprises a pair of amplification cells interconnected at least one interconnection node and connected between a first signal input of a first cell and an output terminal of the second cell, each cell comprising a pair of transistors which have a conduction terminal in common and have the other conduction terminals coupled respectively to a first voltage reference through respective bias members. The structure further comprises a circuit leg connecting a node of the first cell to the output terminal and comprising a transistor which has a control terminal connected to the node of the first cell, a first conduction terminal connected to the output terminal, and a second conduction terminal coupled to a second voltage reference through a capacitor. Thus, a released “zero” can be introduced in the right semiplane of the pole-zero complex plane to improve the flattening of group gain.

摘要翻译： 本发明涉及具有可编程零点的前馈类型的电路结构，特别是用于合成时间连续滤波器。 该结构包括互连至少一个互连节点并连接在第一单元的第一信号输入和第二单元的输出端之间的一对放大单元，每个单元包括一对具有共同的导通端子并具有 其它导电端子通过相应的偏置构件分别耦合到第一电压基准。 所述结构还包括将所述第一单元的节点连接到所述输出端子并且包括具有连接到所述第一单元的节点的控制端子的晶体管，连接到所述输出端子的第一导通端子和第二导通 端子通过电容器耦合到第二参考电压。 因此，可以在极零复平面的右半平面中引入释放的“零”，以改善组增益的平坦化。

公开(公告)号：US06239653B1

公开(公告)日：2001-05-29

申请号：US08984107

申请日：1997-12-03

申请人： Frencesco Rezzi ,  Rinaldo Castello ,  Marco Cazzaniga ,  Ivan Bietti

发明人： Frencesco Rezzi ,  Rinaldo Castello ,  Marco Cazzaniga ,  Ivan Bietti

IPC分类号： H03K500

CPC分类号： H03H11/0433

摘要： The invention relates to an elementary biquadratic cell for programmable time-continuous analog filters. The biquadratic cell is coupled between a first voltage reference and a second voltage reference and has at least one pair of input terminals and first and second pairs of output terminals. The cell includes a pair of half-cells, which half-cells are structurally identical with each other. Each half-cell comprises at least a first transistor coupled between the first and the second voltage reference and having a base terminal connected to a respective one of the input terminals. Each half-cell further comprises second and third transistors coupled between the first and second voltage references. The second transistor has a base terminal connected to the first output terminal of the first pair of output terminals and a collector terminal connected to the first output terminal of the second pair of output terminals. The third transistor has a collector terminal connected to the first output terminal of the first pair of output terminals and a base terminal connected to the second output terminal of the second pair of output terminals.

摘要翻译： 本发明涉及用于可编程时间连续模拟滤波器的基本二次电池。 二次电池耦合在第一参考电压和第二参考电压之间，并且具有至少一对输入端和第一和第二对输出端。 细胞包括一对半细胞，半细胞在结构上彼此相同。 每个半电池包括耦合在第一和第二参考电压之间的至少第一晶体管，并且具有连接到相应输入端子的基极端子。 每个半电池还包括耦合在第一和第二电压基准之间的第二和第三晶体管。 第二晶体管具有连接到第一对输出端子的第一输出端子的基极端子和与第二对输出端子的第一输出端子连接的集电极端子。 第三晶体管具有连接到第一对输出端子的第一输出端子的集电极端子和连接到第二对输出端子的第二输出端子的基极端子。

公开(公告)号：US07573519B2

公开(公告)日：2009-08-11

申请号：US11258812

申请日：2005-10-26

申请人： Christina Phan ,  Marco Cazzaniga

发明人： Christina Phan ,  Marco Cazzaniga

IPC分类号： H04N5/335 ,  H04N9/64 ,  H04N5/217 ,  H01L27/00

CPC分类号： H04N5/3598

摘要： A CMOS image sensor includes a plurality of pixels arranged column and rows in an array; a column circuit for storing reset values and a value after integration; a correlated double sampler which derives an image signal from the reset and the value after integration; and an anti-eclipse circuit physically separately from the column circuit and electrically connected to one or shared between multiple columns of pixels for restoring corrupted column voltage on a column of pixels.

摘要翻译： CMOS图像传感器包括阵列中列和列排列的多个像素; 用于存储复位值的列电路和积分后的值; 相关双采样器，其从复位导出图像信号和积分后的值; 以及与列电路物理分离地电连接到多列像素之间的一个或共享的用于恢复像素列上的损坏的列电压的防蚀电路。

公开(公告)号：US20120154022A1

公开(公告)日：2012-06-21

申请号：US12973493

申请日：2010-12-20

申请人： Marco Cazzaniga ,  Tz-Yi Liu

发明人： Marco Cazzaniga ,  Tz-Yi Liu

IPC分类号： G05F1/10

CPC分类号： H02M3/073 ,  G11C5/145 ,  G11C29/021 ,  H02M2001/008 ,  H02M2003/077

摘要： A multi-stage charge pump selects the number of active stages dynamically. In the exemplary embodiment, this is done by having a multi-stage master charge pump section in which the number of active stages is settable and a slave charge pump section that is of the same design as the master section. The master section is used drive the external load, while the slave section drives an adjustable internal load. The adjustable load is set by control logic by comparing the operation of the two sections. The control logic then operates the slave sections with a different number of active stages than the master stage in order to determine whether the master stage is using the optimal number of active stages. The control logic can then change the number of active stages accordingly.

摘要翻译： 多级电荷泵动态选择有效级数。 在该示例性实施例中，这通过具有其中活动级数可设置的多级主电荷泵部分和与主部分具有相同设计的从电荷泵部分来完成。 主部分用于驱动外部负载，而从部分驱动可调内部负载。 可调负载由控制逻辑通过比较两部分的操作来设定。 然后，控制逻辑以与主级不同的有效级数操作从部件，以便确定主级是使用最佳数量的有效级。 然后，控制逻辑可以相应地改变活动阶段的数量。

公开(公告)号：US07920407B2

公开(公告)日：2011-04-05

申请号：US12395859

申请日：2009-03-02

申请人： Yingchang Chen ,  Marco Cazzaniga

发明人： Yingchang Chen ,  Marco Cazzaniga

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0066 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/72 ,  H03K5/1532

摘要： Circuitry for performing a set or reset process for a reversible resistance-switching memory element in a memory device. A ramped voltage is applied to the memory cell and its state is constantly monitored so that the voltage can be discharged as soon as the set or reset process is completed, avoiding possible disturbs to the memory cell. One set circuit ramps the voltage using a current source, while detecting a current peak using an op-amp loop. One reset circuit ramps the voltage using an op-amp loop, while detecting a current peak by continuing to draw current at the peak current to maintain the output signal stable. Another set circuit ramps the voltage using an op-amp loop and a source-follower configuration. Another reset circuit ramps the voltage using an op-amp loop and a source-follower configuration with level shifting to reduce power consumption. Faster detection and shutoff, and stable operation, are achieved.

摘要翻译： 用于对存储器件中的可逆电阻切换存储元件执行置位或复位处理的电路。 斜坡电压被施加到存储器单元并且其状态被不断地监视，使得一旦设置或复位过程完成就可以将电压放电，避免对存储器单元的可能的干扰。 一个设置电路使用电流源斜坡上升电压，同时使用运算放大器环路检测电流峰值。 一个复位电路使用运算放大器环路来升压电压，同时通过持续在峰值电流下绘制电流来检测电流峰值，以保持输出信号的稳定。 另一个设置电路使用运算放大器回路和源跟随器配置来升压电压。 另一个复位电路使用运算放大器环路和源极跟随器配置，以电平转换来降低电压，从而降低功耗。 实现更快的检测和关断，稳定运行。

公开(公告)号：US08514630B2

公开(公告)日：2013-08-20

申请号：US13016732

申请日：2011-01-28

申请人： Jonathan H. Huynh ,  Feng Pan ,  Viswakiran Popuri ,  Marco Cazzaniga

发明人： Jonathan H. Huynh ,  Feng Pan ,  Viswakiran Popuri ,  Marco Cazzaniga

IPC分类号： G11C11/34

CPC分类号： G11C29/02 ,  G11C16/04 ,  G11C29/025 ,  G11C29/028 ,  G11C2029/5006

摘要： Techniques and corresponding circuitry are presented for the detection of wordline leakage in a memory array. In an exemplary embodiment, a capacitive voltage divider is used to translate the high voltage drop to low voltage drop that can be compared with a reference voltage to determine the voltage drop due to leakage. An on-chip self calibration method can help assure the accuracy of this technique for detecting leakage limit. In other embodiments, the current drawn by a reference array, where a high voltage is applied to the array with all wordlines non-selected, is compared to the current drawn by an array where the high voltage is applied and one or more selected wordlines. In these current based embodiments, the reference array can be a different array, or the same array as that one selected for testing.

摘要翻译： 提供技术和相应的电路用于检测存储器阵列中的字线泄漏。 在示例性实施例中，使用电容分压器将高压降转换成可与参考电压进行比较的低电压降，以确定由于泄漏引起的电压降。 片上自校准方法可以帮助确保这种检测泄漏极限的技术的准确性。 在其他实施例中，将由未被选择的所有字线施加到阵列的高电压的参考阵列绘制的电流与施加高电压的阵列和一个或多个选定的字线所绘制的电流进行比较。 在这些基于当前的实施例中，参考阵列可以是不同的阵列，或与用于测试所选择的阵列相同的阵列。

公开(公告)号：US20100085794A1

公开(公告)日：2010-04-08

申请号：US12395859

申请日：2009-03-02

申请人： Yingchang Chen ,  Marco Cazzaniga

发明人： Yingchang Chen ,  Marco Cazzaniga

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C13/0007 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0066 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/72 ,  H03K5/1532

摘要： Circuitry for performing a set or reset process for a reversible resistance-switching memory element in a memory device. A ramped voltage is applied to the memory cell and its state is constantly monitored so that the voltage can be discharged as soon as the set or reset process is completed, avoiding possible disturbs to the memory cell. One set circuit ramps the voltage using a current source, while detecting a current peak using an op-amp loop. One reset circuit ramps the voltage using an op-amp loop, while detecting a current peak by continuing to draw current at the peak current to maintain the output signal stable. Another set circuit ramps the voltage using an op-amp loop and a source-follower configuration. Another reset circuit ramps the voltage using an op-amp loop and a source-follower configuration with level shifting to reduce power consumption. Faster detection and shutoff, and stable operation, are achieved.

摘要翻译： 用于对存储器件中的可逆电阻切换存储元件执行置位或复位处理的电路。 斜坡电压被施加到存储器单元并且其状态被不断地监视，使得一旦设置或复位过程完成就可以将电压放电，避免对存储器单元的可能的干扰。 一个设置电路使用电流源斜坡上升电压，同时使用运算放大器环路检测电流峰值。 一个复位电路使用运算放大器环路来升压电压，同时通过持续在峰值电流下绘制电流来检测电流峰值，以保持输出信号的稳定。 另一个设置电路使用运算放大器回路和源跟随器配置来升压电压。 另一个复位电路使用运算放大器环路和源极跟随器配置，以电平转换来降低电压，从而降低功耗。 实现更快的检测和关断，稳定运行。

公开(公告)号：US08339185B2

公开(公告)日：2012-12-25

申请号：US12973493

申请日：2010-12-20

申请人： Marco Cazzaniga ,  Tz-Yi Liu

发明人： Marco Cazzaniga ,  Tz-Yi Liu

IPC分类号： G05F1/46 ,  H02M3/18

CPC分类号： H02M3/073 ,  G11C5/145 ,  G11C29/021 ,  H02M2001/008 ,  H02M2003/077

摘要： A multi-stage charge pump selects the number of active stages dynamically. In the exemplary embodiment, this is done by having a multi-stage master charge pump section in which the number of active stages is settable and a slave charge pump section that is of the same design as the master section. The master section is used to drive the external load, while the slave section drives an adjustable internal load. The adjustable internal load is set by control logic by comparing the operation of the two sections. The control logic then operates the slave section with a different number of active stages than the master stage in order to determine whether the master stage is using the optimal number of active stages. The control logic can then change the number of active stages accordingly.

摘要翻译： 多级电荷泵动态选择有效级数。 在该示例性实施例中，这通过具有其中活动级数可设置的多级主电荷泵部分和与主部分具有相同设计的从电荷泵部分来完成。 主部分用于驱动外部负载，而从部分驱动可调内部负载。 可调内部负载由控制逻辑通过比较两部分的操作来设定。 然后，控制逻辑以与主级不同数量的有效级操作从属部分，以便确定主级是否正在使用最佳数量的有效级。 然后，控制逻辑可以相应地改变活动阶段的数量。