公开(公告)号：US07061300B2

公开(公告)日：2006-06-13

申请号：US09797204

申请日：2001-02-27

申请人： Valerio Pisati ,  Marco Cazzaniga ,  Alessandro Venca

发明人： Valerio Pisati ,  Marco Cazzaniga ,  Alessandro Venca

IPC分类号： G05F1/10

CPC分类号： G06G7/163 ,  H03D7/1408 ,  H03D7/1433 ,  H03D7/1491 ,  H03D2200/0086

摘要： The invention relates to a low supply voltage analog multiplier which comprises a pair of differential cells, each cell comprising a pair of bipolar transistors with coupled emitters. A first transistor of each cell receives an input signal on its base terminal and has its collector terminal coupled to a first voltage reference through a bias member. Advantageously, the second transistor of each cell is a diode configuration, and the cells are interconnected at a common node corresponding to the base terminals of the second transistors in each pair. This multiplier can be supplied very low voltages and still exhibit a high rate of operation along with reduced harmonic distortion of the output signal, even with input signals of peak-to-peak amplitude above 600 mV.

摘要翻译： 本发明涉及一种低电源模拟乘法器，其包括一对差分单元，每个单元包括一对具有耦合发射极的双极晶体管。 每个单元的第一晶体管在其基极端子上接收输入信号，并且其集电极端子通过偏置构件耦合到第一电压基准。 有利地，每个单元的第二晶体管是二极管配置，并且这些单元在对应于每对中的第二晶体管的基极端子的公共节点处互连。 该乘法器可以提供非常低的电压，并且仍然表现出高的运行速率以及降低的输出信号的谐波失真，即使高峰值幅度高于600 mV的输入信号也是如此。

公开(公告)号：US08896387B1

公开(公告)日：2014-11-25

申请号：US13330140

申请日：2011-12-19

申请人： Alessandro Venca ,  Enrico Sacchi ,  Sehat Sutardja

发明人： Alessandro Venca ,  Enrico Sacchi ,  Sehat Sutardja

IPC分类号： H03B5/12

CPC分类号： H03B5/1221 ,  H03B5/1212 ,  H03B5/1228 ,  H03B2200/0062 ,  H03B2200/0064

摘要： In one embodiment, a voltage controlled oscillator (VCO) is provided. The VCO includes a tank circuit. Also, the VCO includes a first pair of transistors. The drains of the first pair of transistors are coupled to the tank circuit and the gates of the first pair of transistors are cross-coupled with the drains of the first pair of transistors. The first pair of transistors each have a first threshold voltage. The VCO further includes a second pair of transistors. The drains of the second pair of transistors are respectively coupled to the sources of the first pair of transistors and the gates of the second pair of transistors are respectively coupled to the gates of the first pair of transistors, The second pair of transistors each have a second threshold voltage higher than the first threshold voltage.

摘要翻译： 在一个实施例中，提供压控振荡器（VCO）。 VCO包括一个储能电路。 此外，VCO包括第一对晶体管。 第一对晶体管的漏极耦合到储能电路，第一对晶体管的栅极与第一对晶体管的漏极交叉耦合。 第一对晶体管每个具有第一阈值电压。 VCO还包括第二对晶体管。 第二对晶体管的漏极分别耦合到第一对晶体管的源极，第二对晶体管的栅极分别耦合到第一对晶体管的栅极。第二对晶体管每个具有 第二阈值电压高于第一阈值电压。

公开(公告)号：US07035028B2

公开(公告)日：2006-04-25

申请号：US10843823

申请日：2004-05-12

申请人： Alessandro Venca ,  Roberto Alini ,  Baris Posat

发明人： Alessandro Venca ,  Roberto Alini ,  Baris Posat

IPC分类号： G11B5/09

CPC分类号： G11B5/09 ,  G11B2005/0016 ,  H02M3/073

摘要： A write driver driving a write current through a head connected to the write head by an interconnect. The write driver includes a circuit matching output resistance to the odd characteristic impedance of the interconnect and a voltage boosting circuit. The voltage boosting circuit in connected between a high voltage reference or supply voltage and a low voltage reference, and includes a current source, such as a MOS transistor, connected to the input node of a capacitor. During the overshoot duration, the current source operates at saturation to generate a pulsed current with an amplitude of half the load current. The circuit includes another transistor in series with the current generator between the capacitor and the driver output. A forward bias diode is connected between the capacitor output node and high voltage reference and enters reverse bias during overshoot duration swinging the driver output voltage above supply voltage.

摘要翻译： 一个写入驱动器通过一个连接到写入头的头驱动写入电流。 写驱动器包括匹配输出电阻到互连的奇特特性阻抗的电路和升压电路。 连接在高电压基准或电源电压和低电压基准之间的升压电路，并且包括连接到电容器的输入节点的诸如MOS晶体管的电流源。 在过冲持续时间期间，电流源工作在饱和状态以产生具有一半负载电流幅度的脉冲电流。 电路包括与电容器和驱动器输出之间的电流发生器串联的另一个晶体管。 正向偏置二极管连接在电容器输出节点和高电压基准之间，并在驱动器输出电压高于电源电压的过冲持续时间期间进入反向偏置。

公开(公告)号：US06944834B2

公开(公告)日：2005-09-13

申请号：US10349540

申请日：2003-01-22

申请人： Baris Posat ,  Kemal Ozanoglu ,  Alessandro Venca

发明人： Baris Posat ,  Kemal Ozanoglu ,  Alessandro Venca

IPC分类号： G06F7/60 ,  G06F17/10 ,  G06F17/50

CPC分类号： G06F17/5036

摘要： A method and system are disclosed for generating descriptions of circuits representative of the behavior of dynamic systems. A state space model representing a dynamic system may be used to generate an electronic circuit equivalent having operating characteristics equivalent to the operating characteristics of the dynamic system. The electronic circuit equivalent may be then described as a SPICE circuit description which is simulated to determine the time and frequency domain characteristics of the dynamic system.

摘要翻译： 公开了一种用于生成代表动态系统的行为的电路描述的方法和系统。 可以使用表示动态系统的状态空间模型来产生具有与动态系统的操作特性等效的操作特性的等效电子电路。 然后可以将电子电路等效物描述为SPICE电路描述，其被模拟以确定动态系统的时域和频域特性。

公开(公告)号：US07880545B1

公开(公告)日：2011-02-01

申请号：US12397118

申请日：2009-03-03

申请人： Alessandro Venca ,  Daniele Ottini ,  Francesco Rezzi ,  Rinaldo Castello

发明人： Alessandro Venca ,  Daniele Ottini ,  Francesco Rezzi ,  Rinaldo Castello

IPC分类号： H03F1/14

CPC分类号： H03F3/45475 ,  H03F1/14 ,  H03F1/34 ,  H03F3/3022 ,  H03F2200/153 ,  H03F2200/297

摘要： The present invention provides compensation for circuits. In one embodiment, a compensation circuit has a first terminal coupled to an output terminal of the circuit and a second terminal coupled to feed back the output voltage to an internal node. A damping circuit may also be coupled to the output terminal. The damping circuit adds a pole and a zero to the transfer function of the circuit. In one embodiment, the damping circuit modifies the effect of the output impedance of a load on the transfer function to increase the phase margin of the circuit such that the circuit remains stable over an increased range of output capacitor values.

摘要翻译： 本发明提供对电路的补偿。 在一个实施例中，补偿电路具有耦合到电路的输出端的第一端子和耦合以将输出电压反馈到内部节点的第二端子。 阻尼电路也可以耦合到输出端子。 阻尼电路向电路的传递函数添加极点和零点。 在一个实施例中，阻尼电路改变负载的输出阻抗对传递函数的影响，以增加电路的相位裕度，使得电路在输出电容器值的增加范围内保持稳定。

公开(公告)号：US20060262446A1

公开(公告)日：2006-11-23

申请号：US11438850

申请日：2006-05-23

申请人： Baris Posat ,  Kemal Ozanoglu ,  Alessandro Venca

发明人： Baris Posat ,  Kemal Ozanoglu ,  Alessandro Venca

IPC分类号： G11B5/02

CPC分类号： G11B20/10009 ,  G11B5/02 ,  G11B5/09 ,  G11B2005/0013 ,  G11B2005/0029 ,  H03F1/42 ,  H03F3/45278 ,  H03F2200/36 ,  H03F2200/432 ,  H03F2203/45318 ,  H03F2203/45544 ,  H03F2203/45594 ,  H03F2203/45648

摘要： An amplifying circuit and method are disclosed for amplifying electrical signals, such as electrical signals generated by the read head of a disk drive. The circuit includes a pair of cross-coupled differential amplifier circuits. Each differential amplifier circuit is asymmetric, including two input transistors of different transistor types. For instance, a first of the two input transistors of each differential amplifier circuit may be a bipolar transistor and a second of the two input transistors may be a field effect transistor. By utilizing asymmetric differential amplifier circuits, a relatively wider operating frequency range is obtained.

公开(公告)号：US20050254159A1

公开(公告)日：2005-11-17

申请号：US10843823

申请日：2004-05-12

申请人： Alessandro Venca ,  Roberto Alini ,  Baris Posat

发明人： Alessandro Venca ,  Roberto Alini ,  Baris Posat

IPC分类号： G11B5/09 ,  G05F3/26 ,  G11B5/00 ,  G11B5/02 ,  H02M3/07

CPC分类号： G11B5/09 ,  G11B2005/0016 ,  H02M3/073

摘要： A write driver driving a write current through a head connected to the write head by an interconnect. The write driver includes a circuit matching output resistance to the odd characteristic impedance of the interconnect and a voltage boosting circuit. The voltage boosting circuit in connected between a high voltage reference or supply voltage and a low voltage reference, and includes a current source, such as a MOS transistor, connected to the input node of a capacitor. During the overshoot duration, the current source operates at saturation to generate a pulsed current with an amplitude of half the load current. The circuit includes another transistor in series with the current generator between the capacitor and the driver output. A forward bias diode is connected between the capacitor output node and high voltage reference and enters reverse bias during overshoot duration swinging the driver output voltage above supply voltage.

摘要翻译： 一个写入驱动器通过一个连接到写入头的头驱动写入电流。 写驱动器包括匹配输出电阻到互连的奇特特性阻抗的电路和升压电路。 连接在高电压基准或电源电压和低电压基准之间的升压电路，并且包括连接到电容器的输入节点的诸如MOS晶体管的电流源。 在过冲持续时间期间，电流源工作在饱和状态以产生具有一半负载电流幅度的脉冲电流。 电路包括与电容器和驱动器输出之间的电流发生器串联的另一个晶体管。 正向偏置二极管连接在电容器输出节点和高电压基准之间，并在驱动器输出电压高于电源电压的过冲持续时间期间进入反向偏置。

公开(公告)号：US20050231843A1

公开(公告)日：2005-10-20

申请号：US10824096

申请日：2004-04-14

申请人： Alessandro Venca ,  Roberto Alini ,  Baris Posat

发明人： Alessandro Venca ,  Roberto Alini ,  Baris Posat

IPC分类号： G11B5/09 ,  G05F3/26 ,  G11B5/02 ,  H04L25/02

CPC分类号： G11B5/02

摘要： A write driver for driving a write current through a write head connected to the write head by an interconnect or flexible transmission line. The write driver includes a circuit matching an output impedance of the write driver to the odd characteristic impedance of the interconnect and includes a current source generating a current output to the write head. The write driver provides a current amplification effect as the output current is half the write current driven through the write coil. The impedance matching circuit includes an output resistor with a resistance equal to the odd characteristic impedance of the interconnect. The write driver includes a voltage source that operates to maintain a voltage drop of zero on the output resistor during the initial period of twice the transmission delay of the interconnect.

摘要翻译： 用于通过互连或柔性传输线连接到写入头的写入头来驱动写入电流的写入驱动器。 写驱动器包括将写驱动器的输出阻抗与互连的奇特特性阻抗匹配的电路，并且包括产生到写头的电流输出的电流源。 写入驱动器提供电流放大效应，因为输出电流是通过写入线圈驱动的写入电流的一半。 阻抗匹配电路包括具有等于互连的奇特性阻抗的电阻的输出电阻器。 写入驱动器包括电压源，其操作以在互连的传输延迟的两倍的初始周期期间在输出电阻器上保持零电压降。

公开(公告)号：US08868015B2

公开(公告)日：2014-10-21

申请号：US12782848

申请日：2010-05-19

申请人： Gregory Uehara ,  Chao Yang ,  Ruoxin Jiang ,  Fernando De Bernardinis ,  Alessandro Venca ,  Rinaldo Castello ,  Marc Leroux ,  Brian Brunn

发明人： Gregory Uehara ,  Chao Yang ,  Ruoxin Jiang ,  Fernando De Bernardinis ,  Alessandro Venca ,  Rinaldo Castello ,  Marc Leroux ,  Brian Brunn

IPC分类号： H04B1/04 ,  H04B1/00

CPC分类号： H04B1/0071

摘要： In one embodiment, an apparatus includes an upconversion unit configured to upconvert a baseband signal to a radio frequency (RF) signal. A plurality of baluns for a plurality of wireless bands are provided. Multiplexing circuitry is coupled to the plurality of baluns where the upconversion unit is coupled to each balun through the multiplexing circuitry. The multiplexing circuitry is configured to multiplex the radio frequency signal from the upconversion unit to one of the plurality of baluns based on a wireless band being used.

摘要翻译： 在一个实施例中，一种装置包括上变频单元，其被配置为将基带信号上变频到射频（RF）信号。 提供了多个用于多个无线频段的不平衡变压器。 多路复用电路耦合到多个不平衡转换器，其中上转换单元通过复用电路耦合到每个平衡 - 不平衡变换器。 复用电路被配置为基于所使用的无线频带将来自上变频单元的射频信号复用到多个巴伦中的一个。

公开(公告)号：US08400197B2

公开(公告)日：2013-03-19

申请号：US13191329

申请日：2011-07-26

申请人： Luca Romano ,  Alessandro Venca ,  Stefano Dal Toso ,  Antonio Milani ,  Brian Brunn

发明人： Luca Romano ,  Alessandro Venca ,  Stefano Dal Toso ,  Antonio Milani ,  Brian Brunn

IPC分类号： H03L7/06

CPC分类号： H03L7/08 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0816 ,  H03L7/16 ,  H03L7/1976

摘要： In one embodiment, an apparatus includes a jitter generator configured to receive a reference clock; add jitter to the reference clock; and output the reference clock with the included jitter to a phase lock loop (PLL). The PLL is used to generate a local oscillator (LO) signal for a transceiver. A jitter controller outputs a signal to the jitter generator to control a characteristic of the jitter added to the reference clock. The reference clock with the added jitter is used to reduce a fractional spur caused by a radio frequency (RF) attacker coupling into the PLL.