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1.发明申请公开(公告)号：US20070150759A1
公开(公告)日：2007-06-28
申请号：US11316541
申请日：2005-12-22
申请人： Vasudevan Srinivasan , Susumu Arai , Barnes Cooper
发明人： Vasudevan Srinivasan , Susumu Arai , Barnes Cooper
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/329 , G06F9/4818 , G06F11/3423 , G06F11/3466 , Y02D10/24
摘要： In some embodiments, the method and apparatus to provide for the detection of processor transition states is described. Some embodiments include at least two threads which provide detection for high and low priority states, which provide for power state transitions by the operating system: The low priority thread runs just prior to entry into an idle or low power state; the high priority thread runs when the idle state is ended or the highest power state is reached. In some embodiments, the use of these threads provides for the detection of processor state transitions and idle times independently of the operating system. Other embodiments are described.
摘要翻译： 在一些实施例中，描述了提供用于检测处理器转换状态的方法和装置。 一些实施例包括提供针对高优先级和低优先级状态的检测的至少两个线程，其提供操作系统的功率状态转换：低优先级线程在进入空闲或低功率状态之前运行; 高优先级线程在空闲状态结束或达到最高功率状态时运行。 在一些实施例中，这些线程的使用提供独立于操作系统的处理器状态转换和空闲时间的检测。 描述其他实施例。
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2.发明授权公开(公告)号：US07689838B2
公开(公告)日：2010-03-30
申请号：US11316541
申请日：2005-12-22
申请人： Vasudevan Srinivasan , Susumu Arai , Barnes Cooper
发明人： Vasudevan Srinivasan , Susumu Arai , Barnes Cooper
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/329 , G06F9/4818 , G06F11/3423 , G06F11/3466 , Y02D10/24
摘要： In some embodiments, the method and apparatus to provide for the detection of processor transition states is described. Some embodiments include at least two threads which provide detection for high and low priority states, which provide for power state transitions by the operating system: The low priority thread runs just prior to entry into an idle or low power state; the high priority thread runs when the idle state is ended or the highest power state is reached. In some embodiments, the use of these threads provides for the detection of processor state transitions and idle times independently of the operating system. Other embodiments are described.
摘要翻译： 在一些实施例中，描述了提供用于检测处理器转换状态的方法和装置。 一些实施例包括提供针对高优先级和低优先级状态的检测的至少两个线程，其提供操作系统的功率状态转换：低优先级线程在进入空闲或低功率状态之前运行; 高优先级线程在空闲状态结束或达到最高功率状态时运行。 在一些实施例中，这些线程的使用提供独立于操作系统的处理器状态转换和空闲时间的检测。 描述其他实施例。
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公开(公告)号：US20160252942A1
公开(公告)日：2016-09-01
申请号：US14633438
申请日：2015-02-27
申请人： Ankush Varma , Vasudevan Srinivasan , Eugene Gorbatov , Andrew D. Henroid , Barnes Cooper , David W. Browning , Guy M. Therien , Neil W. Songer , Krishnakanth V. Sistla , James G. Hermerding, II
发明人： Ankush Varma , Vasudevan Srinivasan , Eugene Gorbatov , Andrew D. Henroid , Barnes Cooper , David W. Browning , Guy M. Therien , Neil W. Songer , Krishnakanth V. Sistla , James G. Hermerding, II
CPC分类号： G06F1/263 , G06F1/206 , G06F1/3212 , G06F1/324 , G06F15/00 , Y02D10/126 , Y02D10/16 , Y02D10/174
摘要： In one embodiment, a system includes: a plurality of compute nodes to couple in a chassis; a first shared power supply to provide a baseline power level to the plurality of compute nodes; and an auxiliary power source to provide power to one or more of the plurality of compute nodes during operation at a higher power level than the baseline power level. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，系统包括：多个计算节点，用于耦合在机架中; 第一共享电源，用于向所述多个计算节点提供基线功率电平; 以及辅助电源，用于在比基线功率电平更高的功率电平的操作期间向多个计算节点中的一个或多个提供电力。 描述和要求保护其他实施例。
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公开(公告)号：US07930564B2
公开(公告)日：2011-04-19
申请号：US11496944
申请日：2006-07-31
申请人： Susumu Arai , Michael Walz , Barnes Cooper
发明人： Susumu Arai , Michael Walz , Barnes Cooper
IPC分类号： G06F1/00
CPC分类号： G06F1/3203
摘要： A next idle state for a processor in a system may be determined based on a previous idle period and a previous idle state. The next idle state for the processor may also be determined based on times when interrupts are generated by devices in the system.
摘要翻译： 可以基于先前的空闲时段和先前的空闲状态来确定系统中处理器的下一个空闲状态。 处理器的下一个空闲状态也可以基于系统中的设备产生中断的时间来确定。
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公开(公告)号：US20080028240A1
公开(公告)日：2008-01-31
申请号：US11496944
申请日：2006-07-31
申请人： Susumu Arai , Michael Walz , Barnes Cooper
发明人： Susumu Arai , Michael Walz , Barnes Cooper
IPC分类号： G06F1/00
CPC分类号： G06F1/3203
摘要： A next idle state for a processor in a system may be determined based on a previous idle period and a previous idle state. The next idle state for the processor may also be determined based on times when interrupts are generated by devices in the system.
摘要翻译： 可以基于先前的空闲时段和先前的空闲状态来确定系统中的处理器的下一个空闲状态。 处理器的下一个空闲状态也可以基于系统中的设备产生中断的时间来确定。
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公开(公告)号：US20120102349A1
公开(公告)日：2012-04-26
申请号：US13089669
申请日：2011-04-19
申请人： Susumu Arai , Michael Walz , Barnes Cooper
发明人： Susumu Arai , Michael Walz , Barnes Cooper
IPC分类号： G06F1/32
CPC分类号： G06F1/3203
摘要： A next idle state for a processor in a system may be determined based on a previous idle period and a previous idle state. The next idle state for the processor may also be determined based on times when interrupts are generated by devices in the system.
摘要翻译： 可以基于先前的空闲时段和先前的空闲状态来确定系统中的处理器的下一个空闲状态。 处理器的下一个空闲状态也可以基于系统中的设备产生中断的时间来确定。
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公开(公告)号：US20150169036A1
公开(公告)日：2015-06-18
申请号：US14109388
申请日：2013-12-17
申请人： Inder M. Sodhi , Barnes Cooper , Paul S. Diefenbaugh , Faraz A. Siddiqi , Michael Calyer , Andrew D. Henroid , Ruchika Singh
发明人： Inder M. Sodhi , Barnes Cooper , Paul S. Diefenbaugh , Faraz A. Siddiqi , Michael Calyer , Andrew D. Henroid , Ruchika Singh
CPC分类号： G06F1/3243 , G06F1/3287 , G06F1/329 , G06F9/4893 , Y02D10/171 , Y02D10/24 , Y02D50/20
摘要： In an embodiment, a processor includes a plurality of cores to independently execute instructions, at least one graphics engine to independently execute graphics instructions, and a power controller including an alignment logic to cause at least one workload to be executed on a first core to be rescheduled to a different time to enable the plurality of cores to be active during an active time window and to be in a low power state during an idle time window. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，处理器包括多个核以独立地执行指令，至少一个图形引擎来独立地执行图形指令;以及功率控制器，其包括对准逻辑，以使至少一个工作负载在第一个核上被执行为 重新安排到不同的时间，以使得多个核心在活动时间窗口期间是活动的，并且在空闲时间窗口期间处于低功率状态。 描述和要求保护其他实施例。
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公开(公告)号：US08631257B2
公开(公告)日：2014-01-14
申请号：US13445809
申请日：2012-04-12
IPC分类号： G06F1/16
CPC分类号： G06F1/3203
摘要： Embodiments of a system for receiving power management guidelines from a first plurality of components of a system, and developing a power management policy to manage one or more of a second plurality of components of the system based at least in part on the received power management guidelines. Other embodiments are described.
摘要翻译： 用于从系统的第一多个组件接收功率管理指南的系统的实施例，以及至少部分地基于所接收的功率管理指南来开发用于管理系统的第二多个组件中的一个或多个的功率管理策略 。 描述其他实施例。
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公开(公告)号：US08332675B2
公开(公告)日：2012-12-11
申请号：US13213353
申请日：2011-08-19
申请人： Seh W. Kwa , Robert Gough , Neil Songer , Jaya L. Jeyaseelan , Barnes Cooper , Nilesh V. Shah
发明人： Seh W. Kwa , Robert Gough , Neil Songer , Jaya L. Jeyaseelan , Barnes Cooper , Nilesh V. Shah
CPC分类号： G06F1/3203 , G06F1/3246 , G06F1/329 , Y02D10/24
摘要： In some embodiments, an electronic apparatus comprises at least one processor, a plurality of components, and a policy engine comprising logic to receive latency data from one or more components in the electronic device, compute a minimum latency tolerance value from the latency data, and determine a power management policy from the minimum latency tolerance value.
摘要翻译： 在一些实施例中，电子设备包括至少一个处理器，多个组件以及包括用于从电子设备中的一个或多个组件接收等待时间数据的逻辑的策略引擎，从等待时间数据计算最小等待时间容差值，以及 从最小延迟容限值确定电源管理策略。
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公开(公告)号：US20120198248A1
公开(公告)日：2012-08-02
申请号：US13445809
申请日：2012-04-12
IPC分类号： G06F1/00
CPC分类号： G06F1/3203
摘要： Embodiments of a system for receiving power management guidelines from a first plurality of components of a system, and developing a power management policy to manage one or more of a second plurality of components of the system based at least in part on the received power management guidelines. Other embodiments are described.
摘要翻译： 用于从系统的第一多个组件接收功率管理指南的系统的实施例，以及至少部分地基于所接收的功率管理指南来开发用于管理系统的第二多个组件中的一个或多个的功率管理策略 。 描述其他实施例。
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