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    Controlling Reduced Power States Using Platform Latency Tolerance
    4.
    发明申请
    Controlling Reduced Power States Using Platform Latency Tolerance 有权
    使用平台延迟容限来控制低功耗状态

    公开(公告)号：US20150006923A1

    公开(公告)日：2015-01-01

    申请号：US13927746

    申请日：2013-06-26

    申请人： Barnes Cooper ,  Jeffrey R. Wilcox ,  Michael N. Derr ,  Neil W. Songer ,  Craig S. Forbell

    发明人： Barnes Cooper ,  Jeffrey R. Wilcox ,  Michael N. Derr ,  Neil W. Songer ,  Craig S. Forbell

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3206 ,  G06F1/3234 ,  G06F1/3243 ,  Y02D10/152

    摘要： In an embodiment, a processor includes a plurality of cores and power management logic. The power management logic may be to, in response to a first break event during a reduced power state in the processor, set an exit timer based on a platform latency tolerance, block a first plurality of break events from interrupting the reduced power state, and in response to a expiration of the exit timer, terminate the reduced power state. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，处理器包括多个核心和电源管理逻辑。 功率管理逻辑可以是响应于处理器中的降低功率状态期间的第一中断事件而设置基于平台等待时间容限的退出定时器，阻止第一多个中断事件中断降低的功率状态，以及 响应于退出定时器的到期，终止降低的功率状态。 描述和要求保护其他实施例。

    Method and apparatus for providing for detecting processor state transitions
    9.
    发明申请
    Method and apparatus for providing for detecting processor state transitions 有权
    用于提供检测处理器状态转换的方法和装置

    公开(公告)号：US20070150759A1

    公开(公告)日：2007-06-28

    申请号：US11316541

    申请日：2005-12-22

    申请人： Vasudevan Srinivasan ,  Susumu Arai ,  Barnes Cooper

    发明人： Vasudevan Srinivasan ,  Susumu Arai ,  Barnes Cooper

    IPC分类号： G06F1/26

    CPC分类号： G06F1/3203 ,  G06F1/329 ,  G06F9/4818 ,  G06F11/3423 ,  G06F11/3466 ,  Y02D10/24

    摘要： In some embodiments, the method and apparatus to provide for the detection of processor transition states is described. Some embodiments include at least two threads which provide detection for high and low priority states, which provide for power state transitions by the operating system: The low priority thread runs just prior to entry into an idle or low power state; the high priority thread runs when the idle state is ended or the highest power state is reached. In some embodiments, the use of these threads provides for the detection of processor state transitions and idle times independently of the operating system. Other embodiments are described.

    摘要翻译： 在一些实施例中，描述了提供用于检测处理器转换状态的方法和装置。 一些实施例包括提供针对高优先级和低优先级状态的检测的至少两个线程，其提供操作系统的功率状态转换：低优先级线程在进入空闲或低功率状态之前运行; 高优先级线程在空闲状态结束或达到最高功率状态时运行。 在一些实施例中，这些线程的使用提供独立于操作系统的处理器状态转换和空闲时间的检测。 描述其他实施例。

    Method and apparatus for providing for detecting processor state transitions
    10.
    发明授权
    Method and apparatus for providing for detecting processor state transitions 有权
    用于提供检测处理器状态转换的方法和装置

    公开(公告)号：US07689838B2

    公开(公告)日：2010-03-30

    申请号：US11316541

    申请日：2005-12-22

    申请人： Vasudevan Srinivasan ,  Susumu Arai ,  Barnes Cooper

    发明人： Vasudevan Srinivasan ,  Susumu Arai ,  Barnes Cooper

    IPC分类号： G06F1/00

    CPC分类号： G06F1/3203 ,  G06F1/329 ,  G06F9/4818 ,  G06F11/3423 ,  G06F11/3466 ,  Y02D10/24

    摘要： In some embodiments, the method and apparatus to provide for the detection of processor transition states is described. Some embodiments include at least two threads which provide detection for high and low priority states, which provide for power state transitions by the operating system: The low priority thread runs just prior to entry into an idle or low power state; the high priority thread runs when the idle state is ended or the highest power state is reached. In some embodiments, the use of these threads provides for the detection of processor state transitions and idle times independently of the operating system. Other embodiments are described.

    摘要翻译： 在一些实施例中，描述了提供用于检测处理器转换状态的方法和装置。 一些实施例包括提供针对高优先级和低优先级状态的检测的至少两个线程，其提供操作系统的功率状态转换：低优先级线程在进入空闲或低功率状态之前运行; 高优先级线程在空闲状态结束或达到最高功率状态时运行。 在一些实施例中，这些线程的使用提供独立于操作系统的处理器状态转换和空闲时间的检测。 描述其他实施例。