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1.发明申请公开(公告)号：US20090206447A1
公开(公告)日：2009-08-20
申请号：US12031761
申请日：2008-02-15
IPC分类号： H01L23/525 , H01L21/44
CPC分类号： H01L23/5252 , C25D5/02 , C25D5/10 , C25D21/12 , H01L21/2885 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of a circuit and method for electroplating a feature (e.g., a BEOL anti-fuse device) onto a wafer. The embodiments eliminate the use of a seed layer and, thereby, minimize subsequent processing steps (e.g., etching or chemical mechanical polishing (CMP)). Specifically, the embodiments allow for selective electroplating metal or alloy materials onto an exposed portion of a metal layer in a trench on the front side of a substrate. This is accomplished by providing a unique wafer structure that allows a current path to be established from a power supply through a back side contact and in-substrate electrical connector to the metal layer. During electrodeposition, current flow through the current path can be selectively controlled. Additionally, if the electroplated feature is an anti-fuse device, current flow through this current path can also be selectively controlled in order to program the anti-fuse device.
摘要翻译： 公开了用于将特征（例如，BEOL反熔丝器件）电镀到晶片上的电路和方法的实施例。 这些实施例消除了种子层的使用，从而使随后的处理步骤（例如，蚀刻或化学机械抛光（CMP））最小化。 具体地，实施例允许将金属或合金材料选择性地电镀到衬底前侧的沟槽中的金属层的暴露部分上。 这是通过提供一种独特的晶片结构来实现的，该晶片结构允许从电源通过后侧接触和衬底上的电连接器建立到金属层的电流路径。 在电沉积期间，可以选择性地控制通过电流路径的电流。 此外，如果电镀特征是反熔丝器件，则也可以选择性地控制通过该电流路径的电流，以便编程反熔丝器件。
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2.发明申请公开(公告)号：US20120261795A1
公开(公告)日：2012-10-18
申请号：US13535393
申请日：2012-06-28
IPC分类号： H01L23/525
CPC分类号： H01L23/5252 , C25D5/02 , C25D5/10 , C25D21/12 , H01L21/2885 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of a circuit and method for electroplating a feature (e.g., a BEOL anti-fuse device) onto a wafer. The embodiments eliminate the use of a seed layer and, thereby, minimize subsequent processing steps (e.g., etching or chemical mechanical polishing (CMP)). Specifically, the embodiments allow for selective electroplating metal or alloy materials onto an exposed portion of a metal layer in a trench on the front side of a substrate. This is accomplished by providing a unique wafer structure that allows a current path to be established from a power supply through a back side contact and in-substrate electrical connector to the metal layer. During electrodeposition, current flow through the current path can be selectively controlled. Additionally, if the electroplated feature is an anti-fuse device, current flow through this current path can also be selectively controlled in order to program the anti-fuse device.
摘要翻译： 公开了用于将特征（例如，BEOL反熔丝器件）电镀到晶片上的电路和方法的实施例。 这些实施例消除了种子层的使用，从而使随后的处理步骤（例如，蚀刻或化学机械抛光（CMP））最小化。 具体地，实施例允许将金属或合金材料选择性地电镀到衬底前侧的沟槽中的金属层的暴露部分上。 这是通过提供一种独特的晶片结构来实现的，该晶片结构允许从电源通过后侧接触和衬底上的电连接器建立到金属层的电流路径。 在电沉积期间，可以选择性地控制通过电流路径的电流。 此外，如果电镀特征是反熔丝器件，则也可以选择性地控制通过该电流路径的电流，以便编程反熔丝器件。
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3.发明申请METHOD FOR MONITORING PATTERNING INTEGRITY OF ETCHED OPENINGS AND FORMING CONDUCTIVE STRUCTURES WITH THE OPENINGS 有权用于监测雕刻开口的完整性和形成具有开口的导电结构的方法公开(公告)号：US20090255818A1
公开(公告)日：2009-10-15
申请号：US12101329
申请日：2008-04-11
IPC分类号： H01L21/288
CPC分类号： H01L21/76879 , C25D5/10 , C25D5/12 , C25D7/123 , C25D21/12 , H01L21/2885 , H01L21/76802 , H01L22/14 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of a method that both monitors patterning integrity of etched openings (i.e., ensures that lithographically patterned and etched openings are complete) and forms on-chip conductive structures (e.g., contacts, interconnects, fuses, anti-fuses, capacitors, etc.) within such openings. The method embodiments incorporate an electro-deposition process to provide both the means by which pattern integrity of etched openings can be monitored and also the metallization required for the formation of conductive structures within the openings. Specifically, during the electro-deposition process, electron flow is established by applying a current to the back side of the semiconductor wafer, thus, eliminating the need for a seed layer. Electron flow through the wafer and into the electroplating solution is then monitored and used as an indicator of electroplating in the etched openings and, thereby, as an indicator that the openings are completely etched.
摘要翻译： 公开了一种方法的实施例，两者都监控图案化蚀刻开口的完整性（即，确保光刻图案和蚀刻的开口完整），并且形成片上导电结构（例如，触点，互连，熔断器，抗熔丝，电容器等） 。）在这样的开口内。 该方法实施例包括电沉积工艺，以提供能够监测蚀刻开口的图案完整性的装置以及在开口内形成导电结构所需的金属化。 具体地，在电沉积过程中，通过向半导体晶片的背面施加电流来建立电子流动，从而消除了种子层的需要。 然后监测通过晶片并进入电镀溶液的电子流，并将其用作蚀刻开口中的电镀的指示剂，从而作为开口被完全蚀刻的指示器。
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4.发明授权公开(公告)号：US08674476B2
公开(公告)日：2014-03-18
申请号：US13535393
申请日：2012-06-28
IPC分类号： H01L29/00
CPC分类号： H01L23/5252 , C25D5/02 , C25D5/10 , C25D21/12 , H01L21/2885 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of a circuit and method for electroplating a feature (e.g., a BEOL anti-fuse device) onto a wafer. The embodiments eliminate the use of a seed layer and, thereby, minimize subsequent processing steps (e.g., etching or chemical mechanical polishing (CMP)). Specifically, the embodiments allow for selective electroplating metal or alloy materials onto an exposed portion of a metal layer in a trench on the front side of a substrate. This is accomplished by providing a unique wafer structure that allows a current path to be established from a power supply through a back side contact and in-substrate electrical connector to the metal layer. During electrodeposition, current flow through the current path can be selectively controlled. Additionally, if the electroplated feature is an anti-fuse device, current flow through this current path can also be selectively controlled in order to program the anti-fuse device.
摘要翻译： 公开了用于将特征（例如，BEOL反熔丝器件）电镀到晶片上的电路和方法的实施例。 这些实施例消除了种子层的使用，从而使随后的处理步骤（例如，蚀刻或化学机械抛光（CMP））最小化。 具体地，实施例允许将金属或合金材料选择性地电镀到衬底前侧的沟槽中的金属层的暴露部分上。 这是通过提供一种独特的晶片结构来实现的，该晶片结构允许从电源通过后侧接触和衬底上的电连接器建立到金属层的电流路径。 在电沉积期间，可以选择性地控制通过电流路径的电流。 此外，如果电镀特征是反熔丝器件，则也可以选择性地控制通过该电流路径的电流，以便编程反熔丝器件。
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5.发明授权公开(公告)号：US08242578B2
公开(公告)日：2012-08-14
申请号：US13072023
申请日：2011-03-25
IPC分类号： H01L23/52
CPC分类号： H01L23/5252 , C25D5/02 , C25D5/10 , C25D21/12 , H01L21/2885 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of a circuit and method for electroplating a feature (e.g., a BEOL anti-fuse device) onto a wafer. The embodiments eliminate the use of a seed layer and, thereby, minimize subsequent processing steps (e.g., etching or chemical mechanical polishing (CMP)). Specifically, the embodiments allow for selective electroplating metal or alloy materials onto an exposed portion of a metal layer in a trench on the front side of a substrate. This is accomplished by providing a unique wafer structure that allows a current path to be established from a power supply through a back side contact and in-substrate electrical connector to the metal layer. During electrodeposition, current flow through the current path can be selectively controlled. Additionally, if the electroplated feature is an anti-fuse device, current flow through this current path can also be selectively controlled in order to program the anti-fuse device.
摘要翻译： 公开了用于将特征（例如，BEOL反熔丝器件）电镀到晶片上的电路和方法的实施例。 这些实施例消除了种子层的使用，从而使随后的处理步骤（例如，蚀刻或化学机械抛光（CMP））最小化。 具体地，实施例允许将金属或合金材料选择性地电镀到衬底前侧的沟槽中的金属层的暴露部分上。 这是通过提供一种独特的晶片结构来实现的，该晶片结构允许从电源通过后侧接触和衬底上的电连接器建立到金属层的电流路径。 在电沉积期间，可以选择性地控制通过电流路径的电流。 此外，如果电镀特征是反熔丝器件，则也可以选择性地控制通过该电流路径的电流，以便编程反熔丝器件。
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6.发明申请COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICE WITH AN ELECTROPLATED METAL REPLACEMENT GATE 失效具有电镀金属替代门的补充金属氧化物半导体器件公开(公告)号：US20090275179A1
公开(公告)日：2009-11-05
申请号：US11968885
申请日：2008-01-03
申请人： Veeraraghavan S. Basker , John M. Cotte , Hariklia Deligianni , Toshiharu Furukawa , Vamsi K. Paruchuri , William R. Tonti
发明人： Veeraraghavan S. Basker , John M. Cotte , Hariklia Deligianni , Toshiharu Furukawa , Vamsi K. Paruchuri , William R. Tonti
IPC分类号： H01L21/8238 , H01L21/8234
CPC分类号： H01L21/823842 , H01L29/517 , H01L29/66545
摘要： Disclosed herein are embodiments of a method of forming a complementary metal oxide semiconductor (CMOS) device that has at least one high aspect ratio gate structure with a void-free and seam-free metal gate conductor layer positioned on top of a relatively thin high-k gate dielectric layer. These method embodiments incorporate a gate replacement strategy that uses an electroplating process to fill, from the bottom upward, a high-aspect ratio gate stack opening with a metal gate conductor layer. The source of electrons for the electroplating process is a current passed directly through the back side of the substrate. This eliminates the need for a seed layer and ensures that the metal gate conductor layer will be formed without voids or seams. Furthermore, depending upon the embodiment, the electroplating process is performed under illumination to enhance electron flow to a given area (i.e., to enhance plating) or in darkness to prevent electron flow to a given area (i.e., to prevent plating).
摘要翻译： 本文公开了一种形成互补金属氧化物半导体（CMOS）器件的方法的实施例，该器件具有至少一个高纵横比栅极结构，其中无空隙和无缝的金属栅极导体层位于相对薄的高压 k栅介质层。 这些方法实施例包括栅极替换策略，其使用电镀工艺从底部向上填充具有金属栅极导体层的高纵横比栅极堆叠开口。 用于电镀工艺的电子源是直接通过衬底背面的电流。 这消除了对种子层的需要，并且确保金属栅极导体层将形成为没有空隙或接缝。 此外，根据实施例，电镀工艺在照明下进行，以增强电子流向给定区域（即，为了增强电镀）或在黑暗中以防止电子流向给定区域（即防止电镀）。
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7.发明授权Complementary metal oxide semiconductor device with an electroplated metal replacement gate 失效具有电镀金属置换栅的互补金属氧化物半导体器件公开(公告)号：US07776680B2
公开(公告)日：2010-08-17
申请号：US11968885
申请日：2008-01-03
申请人： Veeraraghavan S. Basker , John M. Cotte , Hariklia Deligianni , Toshiharu Furukawa , Vamsi K. Paruchuri , William R. Tonti
发明人： Veeraraghavan S. Basker , John M. Cotte , Hariklia Deligianni , Toshiharu Furukawa , Vamsi K. Paruchuri , William R. Tonti
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L29/517 , H01L29/66545
摘要： Disclosed herein are embodiments of a method of forming a complementary metal oxide semiconductor (CMOS) device that has at least one high aspect ratio gate structure with a void-free and seam-free metal gate conductor layer positioned on top of a relatively thin high-k gate dielectric layer. These method embodiments incorporate a gate replacement strategy that uses an electroplating process to fill, from the bottom upward, a high-aspect ratio gate stack opening with a metal gate conductor layer. The source of electrons for the electroplating process is a current passed directly through the back side of the substrate. This eliminates the need for a seed layer and ensures that the metal gate conductor layer will be formed without voids or seams. Furthermore, depending upon the embodiment, the electroplating process is performed under illumination to enhance electron flow to a given area (i.e., to enhance plating) or in darkness to prevent electron flow to a given area (i.e., to prevent plating).
摘要翻译： 本文公开了一种形成互补金属氧化物半导体（CMOS）器件的方法的实施例，该器件具有至少一个高纵横比栅极结构，其中无空隙和无缝的金属栅极导体层位于相对薄的高压 k栅介质层。 这些方法实施例包括栅极替换策略，其使用电镀工艺从底部向上填充具有金属栅极导体层的高纵横比栅极堆叠开口。 用于电镀工艺的电子源是直接通过衬底背面的电流。 这消除了对种子层的需要，并且确保金属栅极导体层将形成为没有空隙或接缝。 此外，根据实施例，电镀工艺在照明下进行，以增强电子流向给定区域（即，为了增强电镀）或在黑暗中以防止电子流向给定区域（即防止电镀）。
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8.发明授权Method for monitoring patterning integrity of etched openings and forming conductive structures with the openings 有权用于监测蚀刻开口的图案完整性并与开口形成导电结构的方法公开(公告)号：US08043966B2
公开(公告)日：2011-10-25
申请号：US12101329
申请日：2008-04-11
IPC分类号： H01L21/44
CPC分类号： H01L21/76879 , C25D5/10 , C25D5/12 , C25D7/123 , C25D21/12 , H01L21/2885 , H01L21/76802 , H01L22/14 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of a method that both monitors patterning integrity of etched openings (i.e., ensures that lithographically patterned and etched openings are complete) and forms on-chip conductive structures (e.g., contacts, interconnects, fuses, anti-fuses, capacitors, etc.) within such openings. The method embodiments incorporate an electro-deposition process to provide both the means by which pattern integrity of etched openings can be monitored and also the metallization required for the formation of conductive structures within the openings. Specifically, during the electro-deposition process, electron flow is established by applying a current to the back side of the semiconductor wafer, thus, eliminating the need for a seed layer. Electron flow through the wafer and into the electroplating solution is then monitored and used as an indicator of electroplating in the etched openings and, thereby, as an indicator that the openings are completely etched.
摘要翻译： 公开了一种方法的实施例，两者都监控图案化蚀刻开口的完整性（即，确保光刻图案和蚀刻的开口完整），并且形成片上导电结构（例如，触点，互连，熔断器，抗熔丝，电容器等） 。）在这样的开口内。 该方法实施例包括电沉积工艺，以提供能够监测蚀刻开口的图案完整性的装置以及在开口内形成导电结构所需的金属化。 具体地，在电沉积过程中，通过向半导体晶片的背面施加电流来建立电子流动，从而消除了种子层的需要。 然后监测通过晶片并进入电镀溶液的电子流，并将其用作蚀刻开口中的电镀的指示剂，从而作为开口被完全蚀刻的指示器。
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9.发明申请公开(公告)号：US20110169129A1
公开(公告)日：2011-07-14
申请号：US13072023
申请日：2011-03-25
IPC分类号： H01L23/525
CPC分类号： H01L23/5252 , C25D5/02 , C25D5/10 , C25D21/12 , H01L21/2885 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of a circuit and method for electroplating a feature (e.g., a BEOL anti-fuse device) onto a wafer. The embodiments eliminate the use of a seed layer and, thereby, minimize subsequent processing steps (e.g., etching or chemical mechanical polishing (CMP)). Specifically, the embodiments allow for selective electroplating metal or alloy materials onto an exposed portion of a metal layer in a trench on the front side of a substrate. This is accomplished by providing a unique wafer structure that allows a current path to be established from a power supply through a back side contact and in-substrate electrical connector to the metal layer. During electrodeposition, current flow through the current path can be selectively controlled. Additionally, if the electroplated feature is an anti-fuse device, current flow through this current path can also be selectively controlled in order to program the anti-fuse device.
摘要翻译： 公开了用于将特征（例如，BEOL反熔丝器件）电镀到晶片上的电路和方法的实施例。 这些实施例消除了种子层的使用，从而使随后的处理步骤（例如，蚀刻或化学机械抛光（CMP））最小化。 具体地，实施例允许将金属或合金材料选择性地电镀到衬底前侧的沟槽中的金属层的暴露部分上。 这是通过提供一种独特的晶片结构来实现的，该晶片结构允许从电源通过后侧接触和衬底上的电连接器建立到金属层的电流路径。 在电沉积期间，可以选择性地控制通过电流路径的电流。 此外，如果电镀特征是反熔丝器件，则也可以选择性地控制通过该电流路径的电流，以便编程反熔丝器件。
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10.发明授权公开(公告)号：US07935621B2
公开(公告)日：2011-05-03
申请号：US12031761
申请日：2008-02-15
IPC分类号： H01L21/44
CPC分类号： H01L23/5252 , C25D5/02 , C25D5/10 , C25D21/12 , H01L21/2885 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of a circuit and method for electroplating a feature (e.g., a BEOL anti-fuse device) onto a wafer. The embodiments eliminate the use of a seed layer and, thereby, minimize subsequent processing steps (e.g., etching or chemical mechanical polishing (CMP)). Specifically, the embodiments allow for selective electroplating metal or alloy materials onto an exposed portion of a metal layer in a trench on the front side of a substrate. This is accomplished by providing a unique wafer structure that allows a current path to be established from a power supply through a back side contact and in-substrate electrical connector to the metal layer. During electrodeposition, current flow through the current path can be selectively controlled. Additionally, if the electroplated feature is an anti-fuse device, current flow through this current path can also be selectively controlled in order to program the anti-fuse device.
摘要翻译： 公开了用于将特征（例如，BEOL反熔丝器件）电镀到晶片上的电路和方法的实施例。 这些实施例消除了种子层的使用，从而使随后的处理步骤（例如，蚀刻或化学机械抛光（CMP））最小化。 具体地，实施例允许将金属或合金材料选择性地电镀到衬底前侧的沟槽中的金属层的暴露部分上。 这是通过提供一种独特的晶片结构来实现的，该晶片结构允许从电源通过后侧接触和衬底上的电连接器建立到金属层的电流路径。 在电沉积期间，可以选择性地控制通过电流路径的电流。 此外，如果电镀特征是反熔丝器件，则也可以选择性地控制通过该电流路径的电流，以便编程反熔丝器件。
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