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    Method to achieve STI planarization
    1.
    发明授权
    Method to achieve STI planarization 失效
    实现STI平坦化的方法

    公开(公告)号：US06403484B1

    公开(公告)日：2002-06-11

    申请号：US09803187

    申请日：2001-03-12

    申请人： Victor Seng Keong Lim ,  Lap Chan ,  James Lee ,  Chen Feng ,  Wang Ling Goh

    发明人： Victor Seng Keong Lim ,  Lap Chan ,  James Lee ,  Chen Feng ,  Wang Ling Goh

    IPC分类号： H01L2100

    CPC分类号： H01L21/31056 ,  H01L21/31053 ,  H01L21/76229

    摘要： A method of forming shallow trench isolations is described. A plurality of isolation trenches are etched through a first etch stop layer into the underlying semiconductor substrate. An oxide layer is deposited over the first etch stop layer and within the isolation trenches using a high density plasma chemical vapor deposition process (HDP-CVD) wherein after the oxide layer fills the isolation trenches, the deposition component is discontinued while continuing the sputtering component until corners of the first etch stop layer are exposed at edges of the isolation trenches whereby the oxide layer within the isolation trenches is disconnected from the oxide layer overlying the first etch stop layer. Thereafter, a second etch stop layer is deposited overlying the oxide layer within the isolation trenches, the oxide layer overlying the first etch stop layer, and the exposed first etch stop layer corners. The second etch stop layer is polished away until the oxide layer overlying the first etch stop layer is exposed. The exposed oxide layer overlying the first etch stop layer is removed. The first and second etch stop layers are removed to complete the planarized shallow trench isolation regions in the manufacture of an integrated circuit device.

    摘要翻译： 描述了形成浅沟槽隔离的方法。 通过第一蚀刻停止层将多个隔离沟槽蚀刻到下面的半导体衬底中。 使用高密度等离子体化学气相沉积工艺（HDP-CVD）在第一蚀刻停止层和隔离沟槽内沉积氧化物层，其中在氧化物层填充隔离沟槽之后，沉积组分被中断，同时继续溅射组分 直到第一蚀刻停止层的角部暴露在隔离沟槽的边缘处，由此隔离沟槽内的氧化物层与覆盖在第一蚀刻停止层上的氧化物层断开。 此后，沉积在隔离沟槽内的氧化物层上的第二蚀刻停止层，覆盖在第一蚀刻停止层上的氧化物层和暴露的第一蚀刻停止层拐角。 将第二蚀刻停止层抛光，直到暴露出覆盖在第一蚀刻停止层上的氧化物层。 去除覆盖在第一蚀刻停止层上的暴露的氧化物层。 去除第一和第二蚀刻停止层以在集成电路器件的制造中完成平坦化的浅沟槽隔离区。

    Extended poly buffer STI scheme
    2.
    发明授权
    Extended poly buffer STI scheme 失效

    公开(公告)号：US07060573B2

    公开(公告)日：2006-06-13

    申请号：US09759909

    申请日：2001-01-16

    申请人： Victor Seng Keong Lim ,  Feng Chen ,  Lap Chan ,  Wang Ling Goh

    发明人： Victor Seng Keong Lim ,  Feng Chen ,  Lap Chan ,  Wang Ling Goh

    IPC分类号： H01L21/336

    CPC分类号： H01L21/76232

    摘要： A new method of forming shallow trench isolations has been described. A silicon semiconductor substrate is provided. A silicon nitride layer is deposited overlying the substrate. A polysilicon layer is deposited overlying the silicon nitride layer. An oxidation mask is deposited overlying the polysilicon layer. The oxidation mask, polysilicon layer, silicon nitride layer, and the silicon semiconductor substrate are patterned to form trenches for planned shallow trench isolations. The silicon semiconductor substrate exposed within the trenches is oxidized to form an oxide liner layer within the trenches wherein the oxidation mask prevents oxidation of the polysilicon layer. Thereafter the oxidation mask is removed. A trench oxide layer is deposited overlying the liner oxide layer and filling the trenches. The trench oxide layer and the polysilicon layer are polished down stopping at the silicon nitride layer with a polishing selectivity of oxide to polysilicon to nitride of 4:100:1 wherein dishing is avoided to complete shallow trench isolations in the manufacture of an integrated circuit device.

    Method to prevent CU dishing during damascene formation
    3.
    发明授权
    Method to prevent CU dishing during damascene formation 有权
    防止大马士革形成期间CU凹陷的方法

    公开(公告)号：US06376376B1

    公开(公告)日：2002-04-23

    申请号：US09760165

    申请日：2001-01-16

    申请人： Victor Seng Keong Lim ,  Feng Chen ,  Wang Ling Goh

    发明人： Victor Seng Keong Lim ,  Feng Chen ,  Wang Ling Goh

    IPC分类号： H01L2144

    CPC分类号： H01L21/7684

    摘要： A new method of copper damascene metallization utilizing an additional oxide layer between the nitride and the barrier layers to prevent dishing of the copper line after CMP is described. An insulating layer is provided covering semiconductor device structures in and on a semiconductor substrate. A polish stop layer is deposited overlying the insulating layer. An oxide layer is deposited overlying the polish stop layer. An opening is etched through the oxide layer, the polish stop layer, and the insulating layer to one of the semiconductor device structures. A barrier metal layer is deposited over the surface of the oxide layer and within the opening. A copper layer is deposited over the surface of the barrier metal layer. The copper layer and the barrier metal layer not within the opening are polished away wherein the barrier metal layer polishes more slowly than the copper layer whereby dishing of the copper layer occurs. Thereafter, the oxide layer is polished away stopping at the polish stop layer wherein the oxide layer polishes more quickly than the copper layer whereby the dishing of the copper layer is removed and whereby a hump is formed on the copper layer after the oxide layer is completely polished away. The copper layer is overpolished to remove the hump to complete copper damascene metallization in the fabrication of an integrated circuit.

    摘要翻译： 描述了利用在氮化物和阻挡层之间的附加氧化物层的铜镶嵌金属化的新方法，以防止CMP之后的铜线的凹陷。 提供了覆盖半导体衬底中的半导体器件结构的绝缘层。 覆盖在绝缘层上的抛光阻挡层被沉积。 沉积在抛光停止层上的氧化物层。 通过氧化物层，抛光停止层和绝缘层将开口蚀刻到半导体器件结构之一。 在氧化物层的表面和开口内沉积阻挡金属层。 在阻挡金属层的表面上沉积铜层。 铜层和不在开口内的阻挡金属层被抛光，其中阻挡金属层比铜层抛光得更慢，从而发生铜层的凹陷。 此后，在抛光停止层处停止氧化物层，其中氧化物层比铜层更快地抛光，由此去除铜层的凹陷，并且在氧化物层完全在铜层上形成隆起 抛光 在制造集成电路时，铜层被过度抛光以去除凸起以完成铜镶嵌金属化。

    Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application
    4.
    发明授权
    Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application 有权

    公开(公告)号：US06472697B2

    公开(公告)日：2002-10-29

    申请号：US10140574

    申请日：2002-05-08

    申请人： Yeow Kheng Lim ,  Randall Cher Liang Cha ,  Alex See ,  Wang Ling Goh ,  Victor Seng Keong Lim

    发明人： Yeow Kheng Lim ,  Randall Cher Liang Cha ,  Alex See ,  Wang Ling Goh ,  Victor Seng Keong Lim

    IPC分类号： H01L2710

    CPC分类号： H01L21/76838 ,  H01L23/53219 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of manufacturing conductive lines that are thicker (not wider) in the critical paths areas. We form a plurality of first level conductive lines over a first dielectric layer. The first conductive lines run in a first direction. The first level conductive lines are comprised of a first level first conductive line and a second first level conductive line. We form a second dielectric layer over the first level conductive lines and the first dielectric layer. Next, we form a via opening in the second dielectric layer over a portion of the first level first conductive line. A plug is formed filling the via opening. We form a trench pattern in the second dielectric layer. The trench pattern is comprised of trenches that are approximately orthogonal to the first level conductive lines. We fill the trenches with a conductive material to form supplemental second lines. We form second level conductive lines over the supplemental second lines and the plug. The second level conductive lines are aligned parallel to the supplemental second lines. The supplemental second lines are formed under the critical path areas of the second level conductive lines. The second level conductive lines are not formed to contact the first level conductive lines where a contact is not desired. In the critical path areas of the second level conductive lines, the supplemental second lines underlie the second level conductive lines thereby increasing the effective overall wiring thickness in the critical path area thereby improving performance.

    Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application
    5.
    发明授权
    Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application 失效

    公开(公告)号：US06399471B1

    公开(公告)日：2002-06-04

    申请号：US09783379

    申请日：2001-02-15

    申请人： Yeow Kheng Lim ,  Randall Cher Liang Cha ,  Alex See ,  Wang Ling Goh ,  Victor Seng Keong Lim

    发明人： Yeow Kheng Lim ,  Randall Cher Liang Cha ,  Alex See ,  Wang Ling Goh ,  Victor Seng Keong Lim

    IPC分类号： H01L2144

    CPC分类号： H01L21/76838 ,  H01L23/53219 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of manufacturing conductive lines that are thicker (not wider) in the critical paths areas. We form a plurality of first level conductive lines over a first dielectric layer. The first conductive lines run in a first direction. The first level conductive lines are comprised of a first level first conductive line and a second first level conductive line. We form a second dielectric layer over the first level conductive lines and the first dielectric layer. Next, we form a via opening in the second dielectric layer over a portion of the first level first conductive line. A plug is formed filling the via opening. We form a trench pattern in the second dielectric layer. The trench pattern is comprised of trenches that are approximately orthogonal to the first level conductive lines. We fill the trenches with a conductive material to form supplemental second lines. We form second level conductive lines over the supplemental second lines and the plug. The second level conductive lines are aligned parallel to the supplemental second lines. The supplemental second lines are formed under the critical path areas of the second level conductive lines. The second level conductive lines are not formed to contact the first level conductive lines where a contact is not desired. In the critical path areas of the second level conductive lines, the supplemental second lines underlie the second level conductive lines thereby increasing the effective overall wiring thickness in the critical path area thereby improving performance.

    Shallow trench isolation using TEOS cap and polysilicon pullback
    6.
    发明授权
    Shallow trench isolation using TEOS cap and polysilicon pullback 有权
    浅沟隔离采用TEOS帽和多晶硅回拉

    公开(公告)号：US06613648B1

    公开(公告)日：2003-09-02

    申请号：US10197354

    申请日：2002-07-15

    申请人： Seng-Keong Victor Lim ,  Feng Chen ,  Kong Hean Lee ,  Wang Ling Goh

    发明人： Seng-Keong Victor Lim ,  Feng Chen ,  Kong Hean Lee ,  Wang Ling Goh

    IPC分类号： H01L21762

    CPC分类号： H01L21/76224

    摘要： A method and apparatus for shallow trench isolation. First, a layer of silicon nitride (SiN) is deposited over a semiconductor substrate. A layer of polysilicon is then deposited over the silicon nitride layer. A layer of tetraethylorthosilicate (TEOS) is deposited over the polysilicon layer. Mask and etch steps are performed to form an opening that extends through the TEOS layer and through the polysilicon layer. An etch step is then performed to etch the exposed side surfaces of the polysilicon layer. Thereby, the exposed side surfaces of the polysilicon layer are moved laterally. An etch step is then performed so as to form a trench that extends into the semiconductor substrate. Dielectric material is deposited such that the dielectric material fills the trench and fills the opening that extends through the polysilicon layer and the silicon nitride layer. The substrate is then polished using a chemical mechanical polishing process. The chemical mechanical polishing process removes the polysilicon layer and forms a plug of dielectric material that fills the trench. The plug of dielectric material has a top surface that is planar with respect to the top of the silicon nitride layer.

    摘要翻译： 浅沟槽隔离的方法和装置。 首先，在半导体衬底上沉积氮化硅层（SiN）。 然后在氮化硅层上沉积一层多晶硅。 在多晶硅层上沉积一层原硅酸四乙酯（TEOS）。 执行掩模和蚀刻步骤以形成延伸穿过TEOS层并穿过多晶硅层的开口。 然后执行蚀刻步骤以蚀刻多晶硅层的暴露的侧表面。 由此，多晶硅层的露出侧表面横向移动。 然后执行蚀刻步骤以形成延伸到半导体衬底中的沟槽。 介电材料被沉积成使得介电材料填充沟槽并填充延伸穿过多晶硅层和氮化硅层的开口。 然后使用化学机械抛光工艺抛光衬底。 化学机械抛光工艺去除多晶硅层并形成填充沟槽的电介质材料塞。 电介质材料的插塞具有相对于氮化硅层的顶部是平面的顶表面。

    Method for buffer STI scheme with a hard mask layer as an oxidation barrier
    9.
    发明授权
    Method for buffer STI scheme with a hard mask layer as an oxidation barrier 有权
    具有硬掩模层作为氧化屏障的缓冲STI方案

    公开(公告)号：US06613649B2

    公开(公告)日：2003-09-02

    申请号：US10002873

    申请日：2001-12-05

    申请人： Seng-Keong Victor Lim ,  Feng Chen ,  Alex See ,  Wang Ling Goh

    发明人： Seng-Keong Victor Lim ,  Feng Chen ,  Alex See ,  Wang Ling Goh

    IPC分类号： H01L2176

    CPC分类号： H01L21/76224

    摘要： A method of manufacturing a shallow trench isolation using a polishing step with reduced dishing. A pad layer, a polish stop layer, a buffer layer and a hard mask layer are formed over a substrate. The hard mask layer has a hard mask opening. We etch a trench opening in the buffer layer, the polish stop layer, the pad layer and form a trench in the substrate using the hard mask layer as an etch mask. We form an oxide trench liner layer along the sidewalls of the trench and an oxide buffer liner layer on the sidewalls of the buffer layer using a thermal oxidation. The hard mask layer prevents the oxidation of the top surface of the buffer layer during the oxidation of the oxide trench liner. This prevents the buffer layer from being consumed by the oxidation and leaves the buffer layer to act in the subsequent chemical-mechanical polish (CMP) step. Next, an insulating layer is formed at least partially filling the trench. The insulating layer is chemical-mechanical polished using the polish stop layer as a stop layer. The buffer layer acts to prevent field oxide dishing during the chemical-mechanical polish.

    摘要翻译： 使用具有减少的凹陷的抛光步骤制造浅沟槽隔离的方法。 在衬底上形成焊盘层，抛光停止层，缓冲层和硬掩模层。 硬掩模层具有硬掩模开口。 我们使用硬掩模层作为蚀刻掩模，在缓冲层，抛光停止层，焊盘层中蚀刻沟槽开口，并在衬底中形成沟槽。 我们使用热氧化沿着沟槽的侧壁和缓冲层的侧壁上的氧化物缓冲衬垫层形成氧化物沟槽衬里层。 硬掩模层防止在氧化物沟槽衬垫的氧化期间缓冲层的顶表面的氧化。 这防止缓冲层被氧化消耗，并使缓冲层在随后的化学 - 机械抛光（CMP）步骤中起作用。 接下来，形成至少部分地填充沟槽的绝缘层。 绝缘层使用抛光停止层作为停止层进行化学机械抛光。 缓冲层用于防止化学机械抛光过程中的场氧化物凹陷。