公开(公告)号：US20080246056A1

公开(公告)日：2008-10-09

申请号：US11697806

申请日：2007-04-09

申请人： Victor W. C. Chan ,  Thomas W. Dyer ,  Sunfei Fang ,  Jinghong Li ,  Teck J. Tang ,  Henry K. Utomo ,  Jiang Yan

发明人： Victor W. C. Chan ,  Thomas W. Dyer ,  Sunfei Fang ,  Jinghong Li ,  Teck J. Tang ,  Henry K. Utomo ,  Jiang Yan

IPC分类号： H01L29/778 ,  H01L21/336

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7843

摘要： Methods of forming a suicide in an embedded silicon germanium (eSiGe) source/drain region using a suicide prevention spacer overlapping an interface between the eSiGe and the silicon channel, and a related PFET with an eSiGe source/drain region and a compressive stress liner in close proximity to a silicon channel thereof, are disclosed. In one embodiment, a method includes providing a gate having a nitrogen-containing spacer adjacent thereto and an epitaxially grown silicon germanium (eSiGe) region adjacent to a silicon channel of the gate; removing the nitrogen-containing spacer that does not extend over the interface between the eSiGe source/drain region and the silicon channel; forming a single silicide prevention spacer about the gate, the single silicide prevention spacer overlapping the interface; and forming the silicide in the eSiGe source/drain region using the single silicide prevention spacer to prevent the silicide from forming in at least an extension area of the silicon channel.

摘要翻译： 在嵌入式硅锗（eSiGe）源极/漏极区域中使用与eSiGe和硅沟道之间的界面重叠的防止硅化物的衬垫形成硅化物的方法以及具有eSiGe源极/漏极区域和压应力衬垫的相关PFET 公开了其接近硅通道的方式。 在一个实施例中，一种方法包括提供具有与其相邻的含氮隔离物的栅极和与栅极的硅沟道相邻的外延生长的硅锗（eSiGe）区域; 去除不在eSiGe源极/漏极区域和硅沟道之间的界面上延伸的含氮隔离物; 在栅极周围形成单个硅化物防止间隔物，单个硅化物防止间隔物与界面重叠; 以及使用单个硅化物防止间隔物在eSiGe源极/漏极区域中形成硅化物，以防止硅化物在硅沟道的至少延伸区域中形成。

公开(公告)号：US08198194B2

公开(公告)日：2012-06-12

申请号：US12729486

申请日：2010-03-23

申请人： Jong Ho Yang ,  Hyung-rae Lee ,  Jin-Ping Han ,  Chung Woh Lai ,  Henry K. Utomo ,  Thomas W. Dyer

发明人： Jong Ho Yang ,  Hyung-rae Lee ,  Jin-Ping Han ,  Chung Woh Lai ,  Henry K. Utomo ,  Thomas W. Dyer

IPC分类号： H01L21/311

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/7848

摘要： Methods of forming p-channel MOSFETs use halo-implant steps that are performed relatively early in the fabrication process. These methods include forming a gate electrode having first sidewall spacers thereon, on a semiconductor substrate, and then forming a sacrificial sidewall spacer layer on the gate electrode. A mask layer then patterned on the gate electrode. The sacrificial sidewall spacer layer is selectively etched to define sacrificial sidewall spacers on the first sidewall spacers, using the patterned mask layer as an etching mask. A PFET halo-implant of dopants is then performed into portions of the semiconductor substrate that extend adjacent the gate electrode, using the sacrificial sidewall spacers as an implant mask. Following this implant step, source and drain region trenches are etched into the semiconductor substrate, on opposite sides of the gate electrode. These source and drain region trenches are then filled by epitaxially growing SiGe source and drain regions therein.

摘要翻译： 形成p沟道MOSFET的方法使用在制造过程中相对较早执行的光晕注入步骤。 这些方法包括在半导体衬底上形成其上具有第一侧壁间隔物的栅电极，然后在栅电极上形成牺牲侧壁间隔层。 然后在栅电极上图案化掩模层。 选择性地蚀刻牺牲侧壁间隔层，以使用图案化掩模层作为蚀刻掩模在第一侧壁间隔物上限定牺牲侧壁间隔物。 然后使用牺牲侧壁间隔件作为植入物掩模，将掺杂剂的PFET晕注入物执行到邻近栅电极延伸的部分半导体衬底。 在该注入步骤之后，源极和漏极区沟槽在栅电极的相对侧被蚀刻到半导体衬底中。 然后通过在其中外延生长SiGe源极和漏极区域来填充这些源极和漏极区沟槽。

公开(公告)号：US20110237039A1

公开(公告)日：2011-09-29

申请号：US12729486

申请日：2010-03-23

申请人： Jong-Ho Yang ,  Hyung-rae Lee ,  Jin-Ping Han ,  Chung Woh Lai ,  Henry K. Utomo ,  Thomas W. Dyer

发明人： Jong-Ho Yang ,  Hyung-rae Lee ,  Jin-Ping Han ,  Chung Woh Lai ,  Henry K. Utomo ,  Thomas W. Dyer

IPC分类号： H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/7848

摘要： Methods of forming p-channel MOSFETs use halo-implant steps that are performed relatively early in the fabrication process. These methods include forming a gate electrode having first sidewall spacers thereon, on a semiconductor substrate, and then forming a sacrificial sidewall spacer layer on the gate electrode. A mask layer is then patterned on the gate electrode. The sacrificial sidewall spacer layer is selectively etched to define sacrificial sidewall spacers on the first sidewall spacers, using the patterned mask layer as an etching mask. A PFET halo-implant of dopants is then performed into portions of the semiconductor substrate that extend adjacent the gate electrode, using the sacrificial sidewall spacers as an implant mask. Following this implant step, source and drain region trenches are etched into the semiconductor substrate, on opposite sides of the gate electrode. These source and drain region trenches are then filled by epitaxially growing SiGe source and drain regions therein.

摘要翻译： 形成p沟道MOSFET的方法使用在制造过程中相对较早执行的光晕注入步骤。 这些方法包括在半导体衬底上形成其上具有第一侧壁间隔物的栅电极，然后在栅电极上形成牺牲侧壁间隔层。 然后在栅极电极上形成掩模层。 选择性地蚀刻牺牲侧壁间隔层，以使用图案化掩模层作为蚀刻掩模在第一侧壁间隔物上限定牺牲侧壁间隔物。 然后使用牺牲侧壁间隔件作为植入物掩模，将掺杂剂的PFET晕注入物执行到邻近栅电极延伸的部分半导体衬底。 在该注入步骤之后，源极和漏极区沟槽在栅电极的相对侧被蚀刻到半导体衬底中。 然后通过在其中外延生长SiGe源极和漏极区域来填充这些源极和漏极区沟槽。

公开(公告)号：US20130149830A1

公开(公告)日：2013-06-13

申请号：US13313881

申请日：2011-12-07

申请人： Hwa-Sung RHEE ,  Seung-Chul Lee ,  Chul-Wan An ,  Henry K. Utomo ,  Seong-Dong Kim

发明人： Hwa-Sung RHEE ,  Seung-Chul Lee ,  Chul-Wan An ,  Henry K. Utomo ,  Seong-Dong Kim

IPC分类号： H01L21/336

CPC分类号： H01L27/092 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7845 ,  H01L29/7848

摘要： Methods of forming field effect transistors include selectively etching source and drain region trenches into a semiconductor region using a gate electrode as an etching mask. An epitaxial growth process is performed to fill the source and drain region trenches. Silicon germanium (SiGe) source and drain regions may be formed using an epitaxial growth process. During this growth process, the bottoms and sidewalls of the trenches may be used as “seeds” for the silicon germanium growth. An epitaxial growth step may then be performed to define silicon capping layers on the SiGe source and drain regions.

摘要翻译： 形成场效应晶体管的方法包括使用栅电极作为蚀刻掩模来选择性地将源极和漏极区沟槽刻蚀成半导体区域。 执行外延生长工艺以填充源极和漏极区沟槽。 可以使用外延生长工艺来形成硅锗（SiGe）源极和漏极区。 在该生长过程中，沟槽的底部和侧壁可以用作硅锗生长的“种子”。 然后可以执行外延生长步骤以在SiGe源极和漏极区上限定硅覆盖层。

公开(公告)号：US08138053B2

公开(公告)日：2012-03-20

申请号：US11763561

申请日：2007-06-15

申请人： Henry K. Utomo ,  Shailendra Mishra ,  Lee Wee Teo ,  Jae Gon Lee ,  Shyue Seng Tan

发明人： Henry K. Utomo ,  Shailendra Mishra ,  Lee Wee Teo ,  Jae Gon Lee ,  Shyue Seng Tan

IPC分类号： H01L21/336

CPC分类号： H01L29/7843 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7848

摘要： Embodiments of the invention provide a method of forming a field-effect-transistor (FET). The method includes implanting one or more n-type dopants to create one or more implanted regions with at least a portion of the implanted regions being designated as regions for forming source and drain extensions of the FET; activating the implanted regions; etching with a chlorine based etchant to create openings in the implanted regions, and forming the source and drain extensions by exptaxially growing embedded silicon germanium in the openings. Structure of a semiconductor field-effect-transistor made thereof is also provided.

摘要翻译： 本发明的实施例提供了形成场效应晶体管（FET）的方法。 该方法包括：注入一个或多个n型掺杂剂以产生一个或多个注入区，其中至少一部分注入区被指定为用于形成FET的源极和漏极扩展的区域; 激活植入区域; 用氯气蚀刻剂蚀刻以在注入区域中形成开口，以及通过在开口中外延生长嵌入式硅锗形成源极和漏极延伸部分。 还提供了由其制成的半导体场效应晶体管的结构。

公开(公告)号：US20090029531A1

公开(公告)日：2009-01-29

申请号：US12244944

申请日：2008-10-03

申请人： Haining S. Yang ,  Henry K. Utomo ,  Judson R. Holt

发明人： Haining S. Yang ,  Henry K. Utomo ,  Judson R. Holt

IPC分类号： H01L21/20

CPC分类号： H01L21/84 ,  H01L21/26533 ,  H01L21/823807 ,  H01L27/1203 ,  H01L29/045

摘要： A method for fabricating a hybrid orientation substrate provides for: (1) a horizontal epitaxial augmentation of a masked surface semiconductor layer that leaves exposed a portion of a base semiconductor substrate; and (2) a vertical epitaxial augmentation of the exposed portion of the base semiconductor substrate. The resulting surface semiconductor layer and epitaxial surface semiconductor layer adjoin with an interface that is not perpendicular to the base semiconductor substrate. The method also includes implanting through the surface semiconductor layer and the epitaxial surface semiconductor layer a dielectric forming ion to provide a buried dielectric layer that separates the surface semiconductor layer and the epitaxial surface semiconductor layer from the base semiconductor substrate.

摘要翻译： 一种混合取向基片的制造方法，其特征在于：（1）使基底半导体衬底的一部分露出的被掩膜的表面半导体层的水平外延增强; 和（2）基底半导体衬底的暴露部分的垂直外延增加。 所得到的表面半导体层和外延表面半导体层与不与基底半导体衬底垂直的界面邻接。 该方法还包括通过表面半导体层和外延表面半导体层注入电介质形成离子，以提供将表面半导体层和外延表面半导体层与基底半导体衬底分离的掩埋电介质层。

公开(公告)号：US07482209B2

公开(公告)日：2009-01-27

申请号：US11559151

申请日：2006-11-13

申请人： Haining S. Yang ,  Henry K. Utomo ,  Judson R. Holt

发明人： Haining S. Yang ,  Henry K. Utomo ,  Judson R. Holt

IPC分类号： H01L21/84

CPC分类号： H01L21/84 ,  H01L21/26533 ,  H01L21/823807 ,  H01L27/1203 ,  H01L29/045

摘要： A method for fabricating a hybrid orientation substrate provides for: (1) a horizontal epitaxial augmentation of a masked surface semiconductor layer that leaves exposed a portion of a base semiconductor substrate; and (2) a vertical epitaxial augmentation of the exposed portion of the base semiconductor substrate. The resulting surface semiconductor layer and epitaxial surface semiconductor layer adjoin with an interface that is not perpendicular to the base semiconductor substrate. The method also includes implanting through the surface semiconductor layer and the epitaxial surface semiconductor layer a dielectric forming ion to provide a buried dielectric layer that separates the surface semiconductor layer and the epitaxial surface semiconductor layer from the base semiconductor substrate.

摘要翻译： 一种混合取向基片的制造方法，其特征在于：（1）使基底半导体衬底的一部分露出的被掩膜的表面半导体层的水平外延增强; 和（2）基底半导体衬底的暴露部分的垂直外延增加。 所得到的表面半导体层和外延表面半导体层与不与基底半导体衬底垂直的界面邻接。 该方法还包括通过表面半导体层和外延表面半导体层注入电介质形成离子，以提供将表面半导体层和外延表面半导体层与基底半导体衬底分离的掩埋电介质层。

公开(公告)号：US07176481B2

公开(公告)日：2007-02-13

申请号：US10905598

申请日：2005-01-12

申请人： Huajie Chen ,  Dureseti Chidambarrao ,  Siddhartha Panda ,  Sang-Hyun Oh ,  Henry K. Utomo ,  Werner A. Rausch

发明人： Huajie Chen ,  Dureseti Chidambarrao ,  Siddhartha Panda ,  Sang-Hyun Oh ,  Henry K. Utomo ,  Werner A. Rausch

IPC分类号： H01L29/06

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/7848

摘要： Disclosed is an integrated circuit structure and a method of making such a structure that has a substrate and P-type and N-type transistors on the substrate. The N-type transistor extension and source/drain regions comprise dopants implanted into the substrate. The P-type transistor extension and source/drain regions partially include a strained epitaxial silicon germanium, wherein the strained silicon germanium comprises of two layers, with a top layer that is closer to the gate stack than the bottom layer. The strained silicon germanium is in-situ doped and creates longitudinal stress on the channel region.

摘要翻译： 公开了一种集成电路结构以及在衬底上具有衬底和P型和N型晶体管的结构的方法。 N型晶体管延伸和源极/漏极区域包括注入到衬底中的掺杂剂。 P型晶体管延伸和源极/漏极区域部分地包括应变外延硅锗，其中应变硅锗包括两层，顶层比底层更靠近栅极堆叠。 应变硅锗被原位掺杂并在沟道区域上产生纵向应力。

公开(公告)号：US08685818B2

公开(公告)日：2014-04-01

申请号：US12823168

申请日：2010-06-25

申请人： Huiling Shang ,  Ying Li ,  Henry K. Utomo

发明人： Huiling Shang ,  Ying Li ,  Henry K. Utomo

IPC分类号： H01L29/8605

CPC分类号： H01L28/20 ,  H01L21/76229 ,  H01L27/0629

摘要： Forming a polysilicon embedded resistor within the shallow trench isolations separating the active area of two adjacent devices, minimizing the electrical interaction between two devices and reducing the capacitive coupling or leakage therebetween. The precision polysilicon resistor is formed independently from the formation of gate electrodes by creating a recess region within the STI region when the polysilicon resistor is embedded within the STI recess region. The polysilicon resistor is decoupled from the gate electrode, making it immune to gate electrode related processes. The method forms the polysilicon resistor following the formation of STIs but before the formation of the p-well and n-well implants. In another embodiment the resistor is formed following the formation of the STIs but after the formation of the well implants.

摘要翻译： 在分离两个相邻器件的有源区域的浅沟槽隔离件之间形成多晶硅嵌入式电阻器，最小化两个器件之间的电气相互作用，并减少它们之间的电容耦合或泄漏。 当多晶硅电阻器嵌入STI凹陷区域内时，通过在STI区域内形成凹陷区域，独立于形成栅电极而形成精密多晶硅电阻器。 多晶硅电阻器与栅极电极分离，使其免受与栅电极相关的工艺的影响。 该方法在形成STI之后但在形成p阱和n阱注入之前形成多晶硅电阻器。 在另一个实施例中，在形成STI之后但在形成井注入之后形成电阻器。

公开(公告)号：US08637941B2

公开(公告)日：2014-01-28

申请号：US12943995

申请日：2010-11-11

申请人： Ying Li ,  Henry K. Utomo

发明人： Ying Li ,  Henry K. Utomo

IPC分类号： H01L29/72

CPC分类号： H01L29/401 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76897 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/823871 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656

摘要： A dielectric liner is formed on sidewalls of a gate stack and a lower contact-level dielectric material layer is deposited on the dielectric liner and planarized. The dielectric liner is recessed relative to the top surface of the lower contact-level dielectric material layer and the top surface of the gate stack. A dielectric metal oxide layer is deposited and planarized to form a dielectric metal oxide spacer that surrounds an upper portion of the gate stack. The dielectric metal oxide layer has a top surface that is coplanar with a top surface of the planarized lower contact-level dielectric material layer. Optionally, the conductive material in the gate stack may be replaced. After deposition of at least one upper contact-level dielectric material layer, at least one via hole extending to a semiconductor substrate is formed employing the dielectric metal oxide spacer as a self-aligning structure.

摘要翻译： 电介质衬垫形成在栅叠层的侧壁上，下电触头层介质材料层沉积在电介质衬垫上并进行平面化处理。 电介质衬垫相对于下接触层电介质材料层的顶表面和栅叠层的顶表面凹陷。 沉积并平坦化介电金属氧化物层以形成围绕栅极堆叠的上部的电介质金属氧化物间隔物。 电介质金属氧化物层具有与平坦化的下部接触电介质材料层的顶表面共面的顶表面。 可选地，栅叠层中的导电材料可以被替换。 在沉积至少一个上接触电介质材料层之后，使用介电金属氧化物间隔物作为自对准结构形成延伸到半导体衬底的至少一个通孔。