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    Protection of Secure Electronic Modules Against Attacks
    3.
    发明申请
    Protection of Secure Electronic Modules Against Attacks 失效
    保护安全电子模块免受攻击

    公开(公告)号：US20080222430A1

    公开(公告)日：2008-09-11

    申请号：US11682349

    申请日：2007-03-06

    申请人： Carl U. Buscaglia ,  Vincenzo Condorelli ,  Kevin C. Gotze ,  Nihad Hadzic ,  Donald W. Plass ,  Tamas Visegrady

    发明人： Carl U. Buscaglia ,  Vincenzo Condorelli ,  Kevin C. Gotze ,  Nihad Hadzic ,  Donald W. Plass ,  Tamas Visegrady

    IPC分类号： G06F12/14

    CPC分类号： G06F21/86 ,  G06F2221/2143

    摘要： A method and apparatus is disclosed for preventing the unintended retention of secret data caused by preferred state/burn in secure electronic modules. Sequentially storing the data, and its inverse on alternating clock cycles, and by actively overwriting it to destroy it, prevents SRAM devices from developing a preferred state. By encrypting a relatively large amount of secret data with a master encryption key, and storing said master key in this non-preferred state storage, the electronic module conveniently extends this protection scheme to a large amount of data, without the overhead of investing or actively erasing the larger storage area.

    摘要翻译： 公开了一种用于防止在安全电子模块中由优选状态/烧伤引起的秘密数据的意外保留的方法和装置。 顺序存储数据及其在交替时钟周期上的反相，并通过主动覆盖数据来破坏数据，从而防止SRAM器件发展成优先状态。 通过使用主加密密钥加密相对大量的秘密数据，并将所述主密钥存储在该非优选状态存储器中，电子模块便于将该保护方案扩展到大量的数据，而无需投入或主动地开销 擦除较大的存储区域。

    Protection of secure electronic modules against attacks
    4.
    发明授权
    Protection of secure electronic modules against attacks 失效
    保护安全的电子模块免受攻击

    公开(公告)号：US07953987B2

    公开(公告)日：2011-05-31

    申请号：US11682349

    申请日：2007-03-06

    申请人： Carl U. Buscaglia ,  Vincenzo Condorelli ,  Kevin C. Gotze ,  Nihad Hadzic ,  Donald W. Plass ,  Tamas Visegrady

    发明人： Carl U. Buscaglia ,  Vincenzo Condorelli ,  Kevin C. Gotze ,  Nihad Hadzic ,  Donald W. Plass ,  Tamas Visegrady

    IPC分类号： G06F12/14

    CPC分类号： G06F21/86 ,  G06F2221/2143

    摘要： A method and apparatus is disclosed for preventing the unintended retention of secret data caused by preferred state/burn-in in secure electronic modules. Sequentially storing the data and its inverse on alternating clock cycles, and by actively overwriting it to destroy it, prevents SRAM devices from developing a preferred state. By encrypting a relatively large amount of secret data with a master encryption key, and storing said master key in this non-preferred state storage, the electronic module conveniently extends this protection scheme to a large amount of data, without the overhead of investing or actively erasing the larger storage area.

    摘要翻译： 公开了一种用于防止由安全电子模块中的优选状态/老化引起的秘密数据的意外保留的方法和装置。 在交替的时钟周期内顺序存储数据及其反相，并通过主动覆盖数据来破坏数据，从而防止SRAM器件发展成优先状态。 通过使用主加密密钥加密相对大量的秘密数据，并将所述主密钥存储在该非优选状态存储器中，电子模块便于将该保护方案扩展到大量的数据，而无需投入或主动地开销 擦除较大的存储区域。

    Method of embedding tamper proof layers and discrete components into printed circuit board stack-up
    6.
    发明授权
    Method of embedding tamper proof layers and discrete components into printed circuit board stack-up 有权
    将防篡改层和分立元件嵌入到印刷电路板堆叠中的方法

    公开(公告)号：US07703201B2

    公开(公告)日：2010-04-27

    申请号：US11163609

    申请日：2005-10-25

    申请人： Stefano Sergio Oggioni ,  Vincenzo Condorelli ,  Nihad Hadzic ,  Kevin C. Gotze ,  Tamas Visegrady

    发明人： Stefano Sergio Oggioni ,  Vincenzo Condorelli ,  Nihad Hadzic ,  Kevin C. Gotze ,  Tamas Visegrady

    IPC分类号： H01K3/00

    CPC分类号： H05K3/1258 ,  H05K1/0275 ,  H05K1/095 ,  H05K1/167 ,  H05K3/108 ,  H05K3/28 ,  H05K2201/10151 ,  H05K2203/0568 ,  Y10T29/49155

    摘要： A method for embedding tamper proof layers and discrete components into a printed circuit board stack-up is disclosed. According to this method, a plating mask is applied on a base substrate to cover partially one of its faces. Conductive ink is then spread on this face so as to fill the gap formed by the plating mask. To obtain a uniform distribution of the conductive ink and then gel it, the conductive ink is preferably heated. A dielectric layer is applied on the conductive ink layer and the polymerization process is ended to obtain a strong adhesion between these two layers. In a preferred embodiment, conductive tracks are simultaneously designed on the other face of the base substrate to reduce thermo-mechanical strains and deformations.

    摘要翻译： 公开了一种将防篡改层和分立元件嵌入到印刷电路板叠层中的方法。 根据该方法，将电镀掩模施加在基底基板上以部分地覆盖其一个面。 然后在该表面上扩散导电油墨，以填充由电镀掩模形成的间隙。 为了获得导电油墨的均匀分布，然后使其凝胶化，优选加热导电油墨。 在导电油墨层上施加电介质层，结束聚合过程，以获得这两层之间的强粘合性。 在优选实施例中，导电轨道同时设计在基底基板的另一面上，以减少热机械应变和变形。

    TAMPER-PROOF CAPS FOR LARGE ASSEMBLY
    7.
    发明申请
    TAMPER-PROOF CAPS FOR LARGE ASSEMBLY 失效
    用于大型组装的防篡改剂

    公开(公告)号：US20070038865A1

    公开(公告)日：2007-02-15

    申请号：US11460329

    申请日：2006-07-27

    申请人： Stefano Oggioni ,  Vincenzo Condorelli ,  Nihad Hadzic

    发明人： Stefano Oggioni ,  Vincenzo Condorelli ,  Nihad Hadzic

    IPC分类号： H04L9/00

    CPC分类号： G06F21/87 ,  H01L23/576 ,  H01L2224/16225 ,  H01L2924/15156 ,  H01L2924/3025 ,  H05K1/0275 ,  H05K1/141 ,  H05K2201/0715 ,  H05K2201/10151 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49165 ,  Y10T29/49172 ,  Y10T29/49174

    摘要： A tamper-proof cap adapted to be mounted on a large assembly for shielding a selected area of the large assembly is disclosed. The tamper-proof cap comprises a laminate stack-up structure wherein at least one open chamber is formed. The stack-up structure comprises at least two layers wherein tamper-proof layers are formed on top of the open chamber. A plurality of vias are disposed around the open chamber, forming with said tamper proof layers a tamper-proof structure around said open chamber. The vias are adapted for connecting the tamper-proof layers to the large assembly when the tamper-proof cap is mounted. In a preferred embodiment, the tamper-proof cap further comprises a shielding layer on top of the tamper-proof layer that are preferably done using conductive ink.

    摘要翻译： 公开了一种适于安装在大型组件上用于屏蔽大组件的选定区域的防篡改盖。 防破坏盖包括层压叠层结构，其中形成至少一个开放室。 堆叠结构包括至少两层，其中在敞开室的顶部上形成防篡改层。 多个通孔设置在开放室周围，与所述防篡改层一起形成围绕所述开放室的防篡改结构。 当安装防盗盖时，通孔适于将防篡改层连接到大组件。 在优选实施例中，防篡改帽还包括防篡改层顶部的屏蔽层，其优选地使用导电油墨进行。

    Cryptographic circuit with voltage-based tamper detection and response circuitry
    8.
    发明申请
    Cryptographic circuit with voltage-based tamper detection and response circuitry 审中-公开
    具有基于电压的篡改检测和响应电路的加密电路

    公开(公告)号：US20070255966A1

    公开(公告)日：2007-11-01

    申请号：US11416005

    申请日：2006-05-01

    申请人： Vincenzo Condorelli ,  Kevin Gotze ,  Nihad Hadzic

    发明人： Vincenzo Condorelli ,  Kevin Gotze ,  Nihad Hadzic

    IPC分类号： G06F12/14

    CPC分类号： G06F21/87

    摘要： A cryptographic circuit with voltage island-based tamper detection and response is disclosed. The circuit includes a voltage island having at least one monitoring circuit and a first storage area for security parameters. The circuit also includes a second storage area for key storage and management logic to tamper the security parameters upon detection of an environmental failure.

    摘要翻译： 公开了一种具有电压岛式篡改检测和响应的加密电路。 电路包括具有至少一个监控电路的电压岛和用于安全参数的第一存储区域。 电路还包括用于密钥存储和管理逻辑的第二存储区域，用于在检测到环境故障时篡改安全参数。

    2-D FIFO memory having full-width read/write capability
    9.
    发明授权
    2-D FIFO memory having full-width read/write capability 失效
    具有全宽读/写能力的2-D FIFO存储器

    公开(公告)号：US06556495B2

    公开(公告)日：2003-04-29

    申请号：US09901864

    申请日：2001-07-09

    申请人： Vincenzo Condorelli ,  Nihad Hadzic

    发明人： Vincenzo Condorelli ,  Nihad Hadzic

    IPC分类号： G11C700

    CPC分类号： G06F5/10 ,  G06F5/065

    摘要： An apparatus and method is disclosed for selecting data in a FIFO memory array made up of a plurality of memory cells arranged in rows and columns, where each row of cells has an associated number of word lines selectively addressable by an associated row address, and each column of cells has an associated bit line that provides access to the memory cells of the associated column as enabled by the respective word lines; and the memory array includes an address decoder having an address input for receiving an input address for selecting word lines in accordance with the input address, and a programmable-width vertical pointer for providing read and write input addresses to the address input of the address decoder during associated read and write operations of the memory array, where the programmable-width vertical pointer modifies the read and write addresses during operations of the memory array and provides a FIFO memory functionality.

    摘要翻译： 公开了一种用于在由排列成行和列的多个存储单元组成的FIFO存储器阵列中选择数据的装置和方法，其中每行单元具有可选地由相关行地址可寻址的相关联的字线数， 单元格列具有相关联的位线，其提供对由相应字线启用的关联列的存储器单元的访问; 并且存储器阵列包括地址解码器，其具有地址输入，用于根据输入地址接收用于选择字线的输入地址;以及可编程宽度垂直指示器，用于向地址解码器的地址输入提供读和写输入地址 在存储器阵列的相关读取和写入操作期间，其中可编程宽度的垂直指示器在存储器阵列的操作期间修改读取和写入地址并提供FIFO存储器功能。

    METHOD OF EMBEDDING TAMPER PROOF LAYERS AND DISCRETE COMPONENTS INTO PRINTED CIRCUIT BOARD STACK-UP
    10.
    发明申请
    METHOD OF EMBEDDING TAMPER PROOF LAYERS AND DISCRETE COMPONENTS INTO PRINTED CIRCUIT BOARD STACK-UP 有权
    嵌入式防篡改层的方法和

    公开(公告)号：US20060086534A1

    公开(公告)日：2006-04-27

    申请号：US11163609

    申请日：2005-10-25

    申请人： Stefano Oggioni ,  Vincenzo Condorelli ,  Nihad Hadzic ,  Kevin Gotze ,  Tamas Visegrady

    发明人： Stefano Oggioni ,  Vincenzo Condorelli ,  Nihad Hadzic ,  Kevin Gotze ,  Tamas Visegrady

    IPC分类号： H05K1/11 ,  H01R12/04

    CPC分类号： H05K3/1258 ,  H05K1/0275 ,  H05K1/095 ,  H05K1/167 ,  H05K3/108 ,  H05K3/28 ,  H05K2201/10151 ,  H05K2203/0568 ,  Y10T29/49155

    摘要： A method for embedding tamper proof layers and discrete components into a printed circuit board stack-up is disclosed. According to this method, a plating mask is applied on a base substrate to cover partially one of its faces. Conductive ink is then spread on this face so as to fill the gap formed by the plating mask. To obtain a uniform distribution of the conductive ink and then gel it, the conductive ink is preferably heated. A dielectric layer is applied on the conductive ink layer and the polymerization process is ended to obtain a strong adhesion between these two layers. In a preferred embodiment, conductive tracks are simultaneously designed on the other face of the base substrate to reduce thermo-mechanical strains and deformations.

    摘要翻译： 公开了一种将防篡改层和分立元件嵌入到印刷电路板叠层中的方法。 根据该方法，将电镀掩模施加在基底基板上以部分地覆盖其一个面。 然后在该表面上扩散导电油墨，以填充由电镀掩模形成的间隙。 为了获得导电油墨的均匀分布，然后使其凝胶化，优选加热导电油墨。 在导电油墨层上施加电介质层，结束聚合过程，以获得这两层之间的强粘合性。 在优选实施例中，导电轨道同时设计在基底基板的另一面上，以减少热机械应变和变形。