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公开(公告)号：US20100046300A1
公开(公告)日：2010-02-25
申请号：US12195552
申请日：2008-08-21
IPC分类号： G11C16/06
CPC分类号： G11C11/5628 , G11C16/10 , G11C16/3454 , G11C2211/5621
摘要： Methods for reducing quick charge loss effects, methods for programming, memory devices, memory devices, and memory systems are disclosed. In one such method, a programming pulse is applied to the word line to increase the threshold voltage of the memory cells being programmed. A negative voltage pulse is applied to the word line after the programming pulse to force any electrons trapped in the tunnel oxide of memory cells being programmed back into the tunnel region. After the negative pulse, a program verify operation is performed.
摘要翻译： 公开了减少快速充电损失效应的方法，编程方法，存储器件和存储器系统。 在一种这样的方法中，将编程脉冲施加到字线以增加正被编程的存储器单元的阈值电压。 在编程脉冲之后，将负电压脉冲施加到字线，以将捕获在存储器单元的隧道氧化物中的任何电子强制编程回隧道区域。 在负脉冲之后，执行程序验证操作。
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公开(公告)号：US20120008409A1
公开(公告)日：2012-01-12
申请号：US13236765
申请日：2011-09-20
IPC分类号： G11C16/10
CPC分类号： G11C11/5628 , G11C16/10 , G11C16/3454 , G11C2211/5621
摘要： Methods for reducing quick charge loss effects, methods for programming, memory devices, memory devices, and memory systems are disclosed. In one such method, a programming pulse is applied to the word line to increase the threshold voltage of the memory cells being programmed. A negative voltage pulse is applied to the word line after the programming pulse to force any electrons trapped in the tunnel oxide of memory cells being programmed back into the tunnel region. After the negative pulse, a program verify operation is performed.
摘要翻译： 公开了减少快速充电损失效应的方法，编程方法，存储器件和存储器系统。 在一种这样的方法中，将编程脉冲施加到字线以增加正被编程的存储器单元的阈值电压。 在编程脉冲之后，将负电压脉冲施加到字线，以将捕获在存储器单元的隧道氧化物中的任何电子强制编程回隧道区域。 在负脉冲之后，执行程序验证操作。
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公开(公告)号：US08027200B2
公开(公告)日：2011-09-27
申请号：US12195552
申请日：2008-08-21
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/10 , G11C16/3454 , G11C2211/5621
摘要： Methods for reducing quick charge loss effects, methods for programming, memory devices, memory devices, and memory systems are disclosed. In one such method, a programming pulse is applied to the word line to increase the threshold voltage of the memory cells being programmed. A negative voltage pulse is applied to the word line after the programming pulse to force any electrons trapped in the tunnel oxide of memory cells being programmed back into the tunnel region. After the negative pulse, a program verify operation is performed.
摘要翻译： 公开了减少快速充电损失效应的方法，编程方法，存储器件和存储器系统。 在一种这样的方法中，将编程脉冲施加到字线以增加正被编程的存储器单元的阈值电压。 在编程脉冲之后，将负电压脉冲施加到字线，以将捕获在存储器单元的隧道氧化物中的任何电子强制编程回隧道区域。 在负脉冲之后，执行程序验证操作。
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公开(公告)号：US08213233B2
公开(公告)日：2012-07-03
申请号：US13236765
申请日：2011-09-20
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/10 , G11C16/3454 , G11C2211/5621
摘要： Methods for reducing quick charge loss effects, methods for programming, memory devices, memory devices, and memory systems are disclosed. In one such method, a programming pulse is applied to the word line to increase the threshold voltage of the memory cells being programmed. A negative voltage pulse is applied to the word line after the programming pulse to force any electrons trapped in the tunnel oxide of memory cells being programmed back into the tunnel region. After the negative pulse, a program verify operation is performed.
摘要翻译： 公开了减少快速充电损失效应的方法，编程方法，存储器件和存储器系统。 在一种这样的方法中，将编程脉冲施加到字线以增加正被编程的存储器单元的阈值电压。 在编程脉冲之后，将负电压脉冲施加到字线，以将捕获在存储器单元的隧道氧化物中的任何电子强制编程回隧道区域。 在负脉冲之后，执行程序验证操作。
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公开(公告)号：US20100039864A1
公开(公告)日：2010-02-18
申请号：US12190409
申请日：2008-08-12
申请人： Vishal Sarin , Dzung Nguyen , Jonathan Pabustan , Jung Sheng Hoei , Jason Guo , William Saiki
发明人： Vishal Sarin , Dzung Nguyen , Jonathan Pabustan , Jung Sheng Hoei , Jason Guo , William Saiki
CPC分类号： G11C16/344 , G11C16/0483 , G11C16/3445
摘要： Methods and apparatus are disclosed, such as those involving a flash memory device that includes a memory block. The memory block includes a plurality of data lines extending substantially parallel to one another, and a plurality of memory cells. One such method includes erasing the memory cells; and performing erase verification on the memory cells. The erase verification includes determining one memory cell by one memory cell whether the individual memory cells coupled to one of the data lines have been erased. The method can also include performing a re-erase operation that selectively re-erases unerased memory cells based at least partly on the result of the erase verification.
摘要翻译： 公开了诸如涉及包括存储器块的闪速存储器件的方法和装置。 存储块包括基本上彼此平行延伸的多条数据线，以及多个存储单元。 一种这样的方法包括擦除存储器单元; 并对存储器单元执行擦除验证。 擦除验证包括由一个存储器单元确定耦合到数据线之一中的各个存储器单元是否已经被擦除的一个存储器单元。 该方法还可以包括执行至少部分地基于擦除验证的结果来选择性地重新擦除未故障存储器单元的重擦除操作。
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公开(公告)号：US20060017084A1
公开(公告)日：2006-01-26
申请号：US10897045
申请日：2004-07-22
申请人： Feng Gao , Changyuan Chen , Vishal Sarin , William Saiki , Hieu Tran , Dana Lee
发明人： Feng Gao , Changyuan Chen , Vishal Sarin , William Saiki , Hieu Tran , Dana Lee
IPC分类号： H01L29/76
CPC分类号： H01L27/0805 , H01L27/0811 , H01L29/94
摘要： An integrated MIS capacitor has two substantially identical MIS capacitors. A first capacitor comprises a first region of a first conductivity type adjacent to a channel region of the first conductivity type in a semiconductor substrate. The semiconductor substrate has a second conductivity type. A gate electrode is insulated and spaced apart from the channel region of the first capacitor. The second capacitor is substantially identical to the first capacitor and is formed in the same semiconductor substrate. The gate electrode of the first capacitor is electrically connected to the first region of the second capacitor and the gate electrode of the second capacitor is electrically connected to the first region of the first capacitor. In this manner, the capacitors are connected in an anti-parallel configuration. A capacitor which has high capacitance densities, low process complexity, ambipolar operation, low voltage and temperature coefficient, low external parasitic resistance and capacitance and good matching characteristics for use in analog designs that can be integrated with existing semiconductor processes results.
摘要翻译： 集成的MIS电容器具有两个基本相同的MIS电容器。 第一电容器包括在半导体衬底中与第一导电类型的沟道区相邻的第一导电类型的第一区域。 半导体衬底具有第二导电类型。 栅电极与第一电容器的沟道区隔离并隔开。 第二电容器基本上与第一电容器相同，并且形成在相同的半导体衬底中。 第一电容器的栅电极电连接到第二电容器的第一区域，并且第二电容器的栅极电连接到第一电容器的第一区域。 以这种方式，电容器以反并联配置连接。 具有高电容密度，低工艺复杂性，双极性操作，低电压和温度系数，低外部寄生电阻和电容以及用于可与现有半导体工艺结合的模拟设计的良好匹配特性的电容器。
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公开(公告)号：US07835190B2
公开(公告)日：2010-11-16
申请号：US12190409
申请日：2008-08-12
申请人： Vishal Sarin , Dzung Nguyen , Jonathan Pabustan , Jung Sheng Hoei , Jason Guo , William Saiki
发明人： Vishal Sarin , Dzung Nguyen , Jonathan Pabustan , Jung Sheng Hoei , Jason Guo , William Saiki
IPC分类号： G11C11/34
CPC分类号： G11C16/344 , G11C16/0483 , G11C16/3445
摘要： Methods and apparatus are disclosed, such as those involving a flash memory device that includes a memory block. The memory block includes a plurality of data lines extending substantially parallel to one another, and a plurality of memory cells. One such method includes erasing the memory cells; and performing erase verification on the memory cells. The erase verification includes determining one memory cell by one memory cell whether the individual memory cells coupled to one of the data lines have been erased. The method can also include performing a re-erase operation that selectively re-erases unerased memory cells based at least partly on the result of the erase verification.
摘要翻译： 公开了诸如涉及包括存储器块的闪速存储器件的方法和装置。 存储块包括基本上彼此平行延伸的多条数据线，以及多个存储单元。 一种这样的方法包括擦除存储器单元; 并对存储器单元执行擦除验证。 擦除验证包括由一个存储器单元确定耦合到数据线之一中的各个存储器单元是否已经被擦除的一个存储器单元。 该方法还可以包括执行至少部分地基于擦除验证的结果来选择性地重新擦除未故障存储器单元的重擦除操作。
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公开(公告)号：US08169832B2
公开(公告)日：2012-05-01
申请号：US12909414
申请日：2010-10-21
申请人： Vishal Sarin , Dzung Nguyen , Jonathan Pabustan , Jung Sheng Hoei , Jason Guo , William Saiki
发明人： Vishal Sarin , Dzung Nguyen , Jonathan Pabustan , Jung Sheng Hoei , Jason Guo , William Saiki
IPC分类号： G11C11/34
CPC分类号： G11C16/344 , G11C16/0483 , G11C16/3445
摘要： Methods and apparatus are disclosed, such as those involving a flash memory device that includes a memory block. The memory block includes a plurality of data lines extending substantially parallel to one another, and a plurality of memory cells. One such method includes erasing the memory cells; and performing erase verification on the memory cells. The erase verification includes determining one memory cell by one memory cell whether the individual memory cells coupled to one of the data lines have been erased. The method can also include performing a re-erase operation that selectively re-erases unerased memory cells based at least partly on the result of the erase verification.
摘要翻译： 公开了诸如涉及包括存储器块的闪速存储器件的方法和装置。 存储块包括基本上彼此平行延伸的多条数据线，以及多个存储单元。 一种这样的方法包括擦除存储器单元; 并对存储器单元执行擦除验证。 擦除验证包括由一个存储器单元确定耦合到数据线之一中的各个存储器单元是否已经被擦除的一个存储器单元。 该方法还可以包括执行至少部分地基于擦除验证的结果来选择性地重新擦除未故障存储器单元的重擦除操作。
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公开(公告)号：US20060123280A1
公开(公告)日：2006-06-08
申请号：US10991702
申请日：2004-11-17
申请人： Hieu Tran , Anh Ly , Sang Nguyen , Vishal Sarin , Hung Nguyen , William Saiki , Loc Hoang
发明人： Hieu Tran , Anh Ly , Sang Nguyen , Vishal Sarin , Hung Nguyen , William Saiki , Loc Hoang
IPC分类号： G11C29/00
CPC分类号： G11C11/5621 , G11C16/04 , G11C29/50 , G11C29/50004
摘要： A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system.
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公开(公告)号：US20110032761A1
公开(公告)日：2011-02-10
申请号：US12909414
申请日：2010-10-21
申请人： Vishal Sarin , Dzung Nguyen , Jonathan Pabustan , Jung Sheng Hoei , Jason Guo , William Saiki
发明人： Vishal Sarin , Dzung Nguyen , Jonathan Pabustan , Jung Sheng Hoei , Jason Guo , William Saiki
CPC分类号： G11C16/344 , G11C16/0483 , G11C16/3445
摘要： Methods and apparatus are disclosed, such as those involving a flash memory device that includes a memory block. The memory block includes a plurality of data lines extending substantially parallel to one another, and a plurality of memory cells. One such method includes erasing the memory cells; and performing erase verification on the memory cells. The erase verification includes determining one memory cell by one memory cell whether the individual memory cells coupled to one of the data lines have been erased. The method can also include performing a re-erase operation that selectively re-erases unerased memory cells based at least partly on the result of the erase verification.
摘要翻译： 公开了诸如涉及包括存储器块的闪速存储器件的方法和装置。 存储块包括基本上彼此平行延伸的多条数据线，以及多个存储单元。 一种这样的方法包括擦除存储器单元; 并对存储器单元执行擦除验证。 擦除验证包括由一个存储器单元确定耦合到数据线之一中的各个存储器单元是否已经被擦除的一个存储器单元。 该方法还可以包括执行至少部分地基于擦除验证的结果来选择性地重新擦除未故障存储器单元的重擦除操作。
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