公开(公告)号：US20060003472A1

公开(公告)日：2006-01-05

申请号：US11215778

申请日：2005-08-30

申请人： Vishnu Agarwal ,  Howard Rhodes

发明人： Vishnu Agarwal ,  Howard Rhodes

IPC分类号： H01L21/00 ,  H01L29/76 ,  H01L21/8242

CPC分类号： H01L27/11502 ,  G11C11/22 ,  H01L27/11585 ,  H01L27/1159

摘要： Integrated memory circuits, key components in thousands of electronic and computer products, have been made using ferroelectric materials, which offer faster write cycles and lower power requirements than some other materials. However, the present inventors have recognized, for example, that conventional techniques for working with the polymers produce polymer layers with thickness variations that compromise performance and manufacturing yield. Accordingly, the present inventors devised unique methods and structures for polymer-based ferroelectric memories. One exemplary method entails forming an insulative layer on a substrate, forming two or more first conductive structures, with at least two of the first conductive structures separated by a gap, forming a gap-filling structure within the gap, and forming a polymer-based ferroelectric layer over the gap-filling structure and the first conductive structures. In some embodiments, the gap-filling structure is a polymer, a spin-on-glass, or a flow-fill oxide.

公开(公告)号：US20050032290A1

公开(公告)日：2005-02-10

申请号：US10931513

申请日：2004-09-01

申请人： Vishnu Agarwal ,  Fred Fishburn ,  Rongsheng Yang ,  Howard Rhodes ,  Jeffrey McKee

发明人： Vishnu Agarwal ,  Fred Fishburn ,  Rongsheng Yang ,  Howard Rhodes ,  Jeffrey McKee

IPC分类号： H01L21/762 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L21/823481 ,  H01L21/76232

摘要： Undesirable transistor leakage in transistor structures becomes greatly reduced in substrates having a doped implant region formed via pulling back first and second layers of a process stack. A portion of the substrate, which also has first and second layers deposited thereon, defines the process stack. The dopant is selected having the same n- or p-typing as the substrate. Through etching, the first and second layers of the process stack become pulled back from a trench wall of the substrate to form the implant region. Occupation of the implant region by the dopant prevents undesirable transistor leakage because the electrical characteristics of the implant region are so significantly changed, in comparison to central areas of the substrate underneath the first layer, that the threshold voltage of the implant region is raised to be about equivalent to or greater than the substantially uniform threshold voltage in the central area.

摘要翻译： 在具有通过拉回工艺叠层的第一层和第二层而形成的掺杂注入区的衬底中，晶体管结构中不期望的晶体管泄漏变得大大降低。 衬底的一部分也具有沉积在其上的第一和第二层，限定了工艺叠层。 掺杂剂选择具有与底物相同的n-或p-型。 通过蚀刻，工艺堆叠的第一和第二层从衬底的沟槽壁拉回以形成植入区域。 由掺杂剂对植入区域的占用防止了不期望的晶体管泄漏，因为与第一层下方的衬底的中心区域相比，注入区域的电特性如此显着地改变，使植入区域的阈值电压升高到 约等于或大于中心区域中的基本均匀的阈值电压。

公开(公告)号：US20050031284A1

公开(公告)日：2005-02-10

申请号：US10929271

申请日：2004-08-30

申请人： Guy Blalock ,  Howard Rhodes ,  Vishnu Agarwal ,  Gurtej Sandhu ,  James Foresi ,  Jean-Francois Viens ,  Dale Fried

发明人： Guy Blalock ,  Howard Rhodes ,  Vishnu Agarwal ,  Gurtej Sandhu ,  James Foresi ,  Jean-Francois Viens ,  Dale Fried

IPC分类号： G02B6/12 ,  G02B6/125 ,  G02B6/136 ,  G02F1/01 ,  G02F1/025 ,  G02B6/10

CPC分类号： G02F1/025 ,  G02B6/125 ,  G02B6/136 ,  G02B2006/12107 ,  G02B2006/12164 ,  G02F1/0147 ,  G02F2203/15

摘要： A waveguide and resonator are formed on a lower cladding of a thermo optic device, each having a formation height that is substantially equal. Thereafter, the formation height of the waveguide is attenuated. In this manner, the aspect ratio as between the waveguide and resonator in an area where the waveguide and resonator front or face one another decreases (in comparison to the prior art) thereby restoring the synchronicity between the waveguide and the grating and allowing higher bandwidth configurations to be used. The waveguide attenuation is achieved by photomasking and etching the waveguide after the resonator and waveguide are formed. In one embodiment the photomasking and etching is performed after deposition of the upper cladding. In another, it is performed before the deposition. Thermo optic devices, thermo optic packages and fiber optic systems having these waveguides are also taught.

摘要翻译： 波导和谐振器形成在热光器件的下包层上，每个具有基本相等的形成高度。 此后，波导的形成高度被衰减。 以这种方式，波导和谐振器在波导和谐振器前面或彼此面对的区域（与现有技术相比）中的波导和谐振器之间的纵横比，从而恢复波导和光栅之间的同步性并允许更高的带宽配置 要使用的。 在形成谐振器和波导之后，通过光掩模和蚀刻波导来实现波导衰减。 在一个实施例中，在沉积上部包层之后进行光掩模和蚀刻。 另一方面，它是在沉积之前进行的。 还教导了具有这些波导的热光器件，热光封装和光纤系统。

公开(公告)号：US07750382B2

公开(公告)日：2010-07-06

申请号：US12324083

申请日：2008-11-26

申请人： Howard Rhodes

发明人： Howard Rhodes

IPC分类号： H01L31/062

CPC分类号： H01L27/14609 ,  H01L27/14643 ,  H01L27/14689 ,  H01L31/035272

摘要： A deep implanted region of a first conductivity type located below a transistor array of a pixel sensor cell and adjacent a doped region of a second conductivity type of a photodiode of the pixel sensor cell is disclosed. The deep implanted region reduces surface leakage and dark current and increases the capacitance of the photodiode by acting as a reflective barrier to photo-generated charge in the doped region of the second conductivity type of the photodiode. The deep implanted region also provides improved charge transfer from the charge collection region of the photodiode to a floating diffusion region adjacent the gate of the transfer transistor.

摘要翻译： 公开了一种位于像素传感器单元的晶体管阵列下方并且与像素传感器单元的第二导电类型的光电二极管的掺杂区相邻的第一导电类型的深度注入区域。 深注入区域减小了表面泄漏和暗电流，并且通过在第二导电类型的光电二极管的掺杂区域中作为光生电荷的反射阻挡来增加光电二极管的电容。 深注入区域还提供从光电二极管的电荷收集区域到与传输晶体管的栅极相邻的浮动扩散区域的改进的电荷转移。

公开(公告)号：US20090179296A1

公开(公告)日：2009-07-16

申请号：US12349968

申请日：2009-01-07

申请人： Howard Rhodes ,  Jeff McKee

发明人： Howard Rhodes ,  Jeff McKee

IPC分类号： H01L31/0256

CPC分类号： H01L27/14689 ,  H01L27/14603 ,  H01L27/14609

摘要： A charge storage capacitor which is connected to various light sensitive and/or electrical elements of a CMOS imager, as well as methods of formation, are disclosed. The charge storage capacitor may be formed entirely over a field oxide region of the CMOS imager, entirely over an active area of a pixel sensor cell, or partially over a field oxide region and partially over an active pixel area of a pixel sensor cell.

摘要翻译： 公开了连接到CMOS成像器的各种光敏元件和/或电元件的电荷存储电容器以及形成方法。 电荷存储电容器可以完全在CMOS成像器的场氧化物区域上形成，整个在像素传感器单元的有效区域上，或部分地在场氧化物区域上，部分地在像素传感器单元的有源像素区域上形成。

公开(公告)号：US20090078978A1

公开(公告)日：2009-03-26

申请号：US12324083

申请日：2008-11-26

申请人： Howard Rhodes

发明人： Howard Rhodes

IPC分类号： H01L27/146

CPC分类号： H01L27/14609 ,  H01L27/14643 ,  H01L27/14689 ,  H01L31/035272

摘要： A deep implanted region of a first conductivity type located below a transistor array of a pixel sensor cell and adjacent a doped region of a second conductivity type of a photodiode of the pixel sensor cell is disclosed. The deep implanted region reduces surface leakage and dark current and increases the capacitance of the photodiode by acting as a reflective barrier to photo-generated charge in the doped region of the second conductivity type of the photodiode. The deep implanted region also provides improved charge transfer from the charge collection region of the photodiode to a floating diffusion region adjacent the gate of the transfer transistor.

摘要翻译： 公开了一种位于像素传感器单元的晶体管阵列下方并且与像素传感器单元的第二导电类型的光电二极管的掺杂区相邻的第一导电类型的深度注入区域。 深注入区域减小了表面泄漏和暗电流，并且通过在第二导电类型的光电二极管的掺杂区域中作为光生电荷的反射阻挡来增加光电二极管的电容。 深注入区域还提供从光电二极管的电荷收集区域到与传输晶体管的栅极相邻的浮动扩散区域的改进的电荷转移。

公开(公告)号：US07470560B2

公开(公告)日：2008-12-30

申请号：US11434767

申请日：2006-05-17

申请人： Howard Rhodes ,  Chandra Mouli

发明人： Howard Rhodes ,  Chandra Mouli

IPC分类号： H01L21/00

CPC分类号： H01L27/14609 ,  H01L27/14643 ,  H01L27/14689 ,  H01L31/035272

摘要： A deep implanted region of a first conductivity type located below a transistor array of a pixel sensor cell and adjacent a doped region of a second conductivity type of a photodiode of the pixel sensor cell is disclosed. The deep implanted region reduces surface leakage and dark current and increases the capacitance of the photodiode by acting as a reflective barrier to photo-generated charge in the doped region of the second conductivity type of the photodiode. The deep implanted region also provides improved charge transfer from the charge collection region of the photodiode to a floating diffusion region adjacent the gate of the transfer transistor.

摘要翻译： 公开了一种位于像素传感器单元的晶体管阵列下方并且与像素传感器单元的第二导电类型的光电二极管的掺杂区相邻的第一导电类型的深度注入区域。 深注入区域减小了表面泄漏和暗电流，并且通过在第二导电类型的光电二极管的掺杂区域中作为光生电荷的反射阻挡来增加光电二极管的电容。 深注入区域还提供从光电二极管的电荷收集区域到与传输晶体管的栅极相邻的浮动扩散区域的改进的电荷转移。

公开(公告)号：US07303938B2

公开(公告)日：2007-12-04

申请号：US10771290

申请日：2004-02-05

申请人： Chandra Mouli ,  Howard Rhodes

发明人： Chandra Mouli ,  Howard Rhodes

IPC分类号： H01L29/762 ,  H01L21/339

CPC分类号： H01L27/14609 ,  H01L27/14603 ,  H01L27/1463 ,  H01L27/14643 ,  H01L27/14689

摘要： Isolation methods and devices for isolating pixels of an image sensor pixel. The isolation structure and methods include forming a biased gate over a field isolation region and adjacent a pixel of an image sensor. The isolation methods also include forming an isolation gate over substantial portions of a field isolation region to isolate pixels in an array of pixels.

摘要翻译： 用于隔离图像传感器像素的像素的隔离方法和设备。 隔离结构和方法包括在场隔离区域上形成偏置栅极并邻近图像传感器的像素。 隔离方法还包括在场隔离区域的大部分上形成隔离栅极以隔离像素阵列中的像素。

公开(公告)号：US20070205447A1

公开(公告)日：2007-09-06

申请号：US11797756

申请日：2007-05-07

申请人： Howard Rhodes

发明人： Howard Rhodes

IPC分类号： H01L31/062

CPC分类号： H01L27/14603 ,  H01L27/14609 ,  H01L27/14641 ,  H01L27/14643 ,  H04N5/376

摘要： An imaging device formed as a CMOS semiconductor integrated circuit having two adjacent pixels in a row connected to a common column line. By having adjacent pixels of a row share column lines, the CMOS imager circuit eliminates half the column lines of a traditional imager allowing the fabrication of a smaller imager. The imaging device also may be fabricated to have a diagonal active area to facilitate contact of two adjacent pixels with the single column line and allow linear row select lines, reset lines and column lines.

摘要翻译： 一种成像装置，其形成为具有连接到公共列线的行中的两个相邻像素的CMOS半导体集成电路。 通过使行的相邻像素共享列线，CMOS成像器电路消除了允许制造较小成像器的传统成像器的一半列线。 成像装置还可以被制造成具有对角线有源区域以促进两个相邻像素与单列线的接触，并允许线性行选择线，复位线和列线。

公开(公告)号：US20070200181A1

公开(公告)日：2007-08-30

申请号：US11797194

申请日：2007-05-01

申请人： Howard Rhodes

发明人： Howard Rhodes

IPC分类号： H01L29/76

CPC分类号： H01L27/14683 ,  H01L27/14609 ,  H01L27/14636 ,  H01L27/14643

摘要： A pixel cell having a photo-conversion device at a surface of a substrate and at least one contact area from which charge or a signal is output or received. A first insulating layer is located over the photo-conversion device and the at least one contact area. The pixel cell further includes at least one conductor in contact with the at least one contact area. The conductor includes a polysilicon material extending through the first insulating layer and in contact with the at least one contact area. Further, a conductive material, which includes at least one of a silicide and a refractory metal, can be over and in contact with the polysilicon material.