公开(公告)号：US20050031284A1

公开(公告)日：2005-02-10

申请号：US10929271

申请日：2004-08-30

申请人： Guy Blalock ,  Howard Rhodes ,  Vishnu Agarwal ,  Gurtej Sandhu ,  James Foresi ,  Jean-Francois Viens ,  Dale Fried

发明人： Guy Blalock ,  Howard Rhodes ,  Vishnu Agarwal ,  Gurtej Sandhu ,  James Foresi ,  Jean-Francois Viens ,  Dale Fried

IPC分类号： G02B6/12 ,  G02B6/125 ,  G02B6/136 ,  G02F1/01 ,  G02F1/025 ,  G02B6/10

CPC分类号： G02F1/025 ,  G02B6/125 ,  G02B6/136 ,  G02B2006/12107 ,  G02B2006/12164 ,  G02F1/0147 ,  G02F2203/15

摘要： A waveguide and resonator are formed on a lower cladding of a thermo optic device, each having a formation height that is substantially equal. Thereafter, the formation height of the waveguide is attenuated. In this manner, the aspect ratio as between the waveguide and resonator in an area where the waveguide and resonator front or face one another decreases (in comparison to the prior art) thereby restoring the synchronicity between the waveguide and the grating and allowing higher bandwidth configurations to be used. The waveguide attenuation is achieved by photomasking and etching the waveguide after the resonator and waveguide are formed. In one embodiment the photomasking and etching is performed after deposition of the upper cladding. In another, it is performed before the deposition. Thermo optic devices, thermo optic packages and fiber optic systems having these waveguides are also taught.

摘要翻译： 波导和谐振器形成在热光器件的下包层上，每个具有基本相等的形成高度。 此后，波导的形成高度被衰减。 以这种方式，波导和谐振器在波导和谐振器前面或彼此面对的区域（与现有技术相比）中的波导和谐振器之间的纵横比，从而恢复波导和光栅之间的同步性并允许更高的带宽配置 要使用的。 在形成谐振器和波导之后，通过光掩模和蚀刻波导来实现波导衰减。 在一个实施例中，在沉积上部包层之后进行光掩模和蚀刻。 另一方面，它是在沉积之前进行的。 还教导了具有这些波导的热光器件，热光封装和光纤系统。

公开(公告)号：US20060234465A1

公开(公告)日：2006-10-19

申请号：US11452816

申请日：2006-06-13

申请人： Vishnu Agarwal ,  Gurtej Sandhu

发明人： Vishnu Agarwal ,  Gurtej Sandhu

IPC分类号： H01L21/44

CPC分类号： H01L28/75 ,  C23C16/34 ,  C23C16/56 ,  H01L21/28568 ,  H01L21/76856 ,  H01L21/76862 ,  H01L21/76868 ,  H01L21/7687 ,  H01L27/1085 ,  H01L28/55 ,  H01L2221/1078

摘要： In one aspect, the invention includes a method of forming a material comprising tungsten and nitrogen, comprising: a) providing a substrate; b) depositing a layer comprising tungsten and nitrogen over the substrate; and c) in a separate step from the depositing, exposing the layer comprising tungsten and nitrogen to a nitrogen-containing plasma. In another aspect, the invention includes a method of forming a capacitor, comprising: a) forming a first electrical node; b) forming a dielectric layer over the first electrical node; c) forming a second electrical node; and d) providing a layer comprising tungsten and nitrogen between the dielectric layer and one of the electrical nodes, the providing comprising; i) depositing a layer comprising tungsten and nitrogen; and ii) in a separate step from the depositing, exposing the layer comprising tungsten and nitrogen to a nitrogen-containing plasma.

公开(公告)号：US20050266624A1

公开(公告)日：2005-12-01

申请号：US11119370

申请日：2005-04-29

申请人： Vishnu Agarwal ,  Gurtej Sandhu

发明人： Vishnu Agarwal ,  Gurtej Sandhu

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/532 ,  H01L29/49

CPC分类号： H01L21/28088 ,  H01L21/28061 ,  H01L21/76841 ,  H01L23/53257 ,  H01L29/4941 ,  H01L29/4966 ,  H01L2924/0002 ,  H01L2924/00

摘要： A diffusion barrier layer comprising TiNxBy is disclosed for protection of gate oxide layers in integrated transistors. The diffusion barrier layer can be fabricated by first forming a TiN layer and then incorporating boron into the TiN layer. The diffusion barrier layer can also be fabricated by forming a TiNxBy layer using a TDMAT process including boron. The diffusion barrier layer can also be fabricated by forming a TiNxBy layer using a CVD process. The diffusion barrier layer is of particular utility in conjunction with tungsten or tungsten silicide conductive layers formed by CVD.

摘要翻译： 公开了一种包括TiN x B B y y的扩散阻挡层，用于保护集成晶体管中的栅极氧化物层。 可以通过首先形成TiN层然后将硼掺入到TiN层中来制造扩散阻挡层。 扩散阻挡层也可以通过使用包括硼的TDMAT工艺来形成TiN层的方法来制造。 扩散阻挡层也可以通过使用CVD工艺形成TiN x B层Y 3层来制造。 扩散阻挡层特别适用于通过CVD形成的钨或硅化钨导电层。

公开(公告)号：US20060261421A1

公开(公告)日：2006-11-23

申请号：US11493458

申请日：2006-07-25

申请人： Vishnu Agarwal ,  Gurtej Sandhu

发明人： Vishnu Agarwal ,  Gurtej Sandhu

IPC分类号： H01L29/94

CPC分类号： H01L21/28088 ,  H01L21/28061 ,  H01L21/76841 ,  H01L23/53257 ,  H01L29/4941 ,  H01L29/4966 ,  H01L2924/0002 ,  H01L2924/00

摘要： A diffusion barrier layer comprising TiNxBy is disclosed for protection of gate oxide layers in integrated transistors. The diffusion barrier layer can be fabricated by first forming a TiN layer and then incorporating boron into the TiN layer. The diffusion barrier layer can also be fabricated by forming a TiNxBy layer using a TDMAT process including boron. The diffusion barrier layer can also be fabricated by forming a TiNxBy layer using a CVD process. The diffusion barrier layer is of particular utility in conjunction with tungsten or tungsten silicide conductive layers formed by CVD.

公开(公告)号：US20060076597A1

公开(公告)日：2006-04-13

申请号：US11235866

申请日：2005-09-26

申请人： Vishnu Agarwal ,  Garo Derderian ,  Gurtej Sandhu ,  Weimin Li ,  Mark Visokay ,  Cem Basceri ,  Sam Yang

发明人： Vishnu Agarwal ,  Garo Derderian ,  Gurtej Sandhu ,  Weimin Li ,  Mark Visokay ,  Cem Basceri ,  Sam Yang

IPC分类号： H01L29/94

CPC分类号： H01L28/84 ,  H01L21/02183 ,  H01L21/02197 ,  H01L21/31637 ,  H01L28/55 ,  H01L28/65

摘要： Capacitors having increased capacitance include an enhanced-surface-area (rough-surfaced) electrically conductive layer or other layers that are compatible with the high-dielectric constant materials. In one approach, an enhanced-surface-area electrically conductive layer for such capacitors is formed by processing a ruthenium oxide layer at high temperature at or above 500° C. and low pressure 75 torr or below, most desirably 5 torr or below, to produce a roughened ruthenium layer having a textured surface with a mean feature size of at least about 100 Angstroms. The initial ruthenium oxide layer may be provided by chemical vapor deposition techniques or sputtering techniques or the like. The layer may be formed over an underlying electrically conductive layer. The processing may be performed in an inert ambient or in a reducing ambient. A nitrogen-supplying ambient or nitrogen-supplying reducing ambient may be used during the processing or afterwards to passivate the ruthenium for improved compatibility with high-dielectric-constant dielectric materials. Processing in an oxidizing ambient may also be performed to passivate the roughened layer. The roughened layer of ruthenium may be used to form an enhanced-surface-area electrically conductive layer. The resulting enhanced-surface-area electrically conductive layer may form a plate of a storage capacitor in an integrated circuit, such as in a memory cell of a DRAM or the like. In another approach, a tungsten nitride layer is provided as an first electrode of such a capacitor. The capacitor, or at least the tungsten nitride layer, is annealed to increase the capacitance of the capacitor.

公开(公告)号：US20050093052A1

公开(公告)日：2005-05-05

申请号：US10973343

申请日：2004-10-27

申请人： Vishnu Agarwal ,  Gurtej Sandhu

发明人： Vishnu Agarwal ,  Gurtej Sandhu

IPC分类号： H01L21/02 ,  H01L21/20 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10817 ,  H01L21/7682 ,  H01L27/0207 ,  H01L27/10852 ,  H01L28/90 ,  H01L28/91

摘要： Structurally-stable, tall capacitors having unique three-dimensional architectures for semiconductor devices are disclosed. The capacitors include monolithically-fabricated upright microstructures, i.e., those having large height/width (H/W) ratios, which are mechanical reinforcement against shear forces and the like, by a brace layer that transversely extends between lateral sides of at least two of the free-standing microstructures. The brace layer is formed as a microbridge type structure spanning between the upper ends of the two or more microstructures.

摘要翻译： 公开了具有用于半导体器件的独特三维结构的结构稳定的高电容器。 这些电容器包括单片制造的直立微结构，即具有大的高/宽（H / W）比的那些，它们是抗剪切力等的机械加强，该支撑层横向延伸在至少两个 独立的微结构。 支撑层形成为跨越两个或更多个微结构的上端之间的微桥型结构。

公开(公告)号：US20050032290A1

公开(公告)日：2005-02-10

申请号：US10931513

申请日：2004-09-01

申请人： Vishnu Agarwal ,  Fred Fishburn ,  Rongsheng Yang ,  Howard Rhodes ,  Jeffrey McKee

发明人： Vishnu Agarwal ,  Fred Fishburn ,  Rongsheng Yang ,  Howard Rhodes ,  Jeffrey McKee

IPC分类号： H01L21/762 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L21/823481 ,  H01L21/76232

摘要： Undesirable transistor leakage in transistor structures becomes greatly reduced in substrates having a doped implant region formed via pulling back first and second layers of a process stack. A portion of the substrate, which also has first and second layers deposited thereon, defines the process stack. The dopant is selected having the same n- or p-typing as the substrate. Through etching, the first and second layers of the process stack become pulled back from a trench wall of the substrate to form the implant region. Occupation of the implant region by the dopant prevents undesirable transistor leakage because the electrical characteristics of the implant region are so significantly changed, in comparison to central areas of the substrate underneath the first layer, that the threshold voltage of the implant region is raised to be about equivalent to or greater than the substantially uniform threshold voltage in the central area.

摘要翻译： 在具有通过拉回工艺叠层的第一层和第二层而形成的掺杂注入区的衬底中，晶体管结构中不期望的晶体管泄漏变得大大降低。 衬底的一部分也具有沉积在其上的第一和第二层，限定了工艺叠层。 掺杂剂选择具有与底物相同的n-或p-型。 通过蚀刻，工艺堆叠的第一和第二层从衬底的沟槽壁拉回以形成植入区域。 由掺杂剂对植入区域的占用防止了不期望的晶体管泄漏，因为与第一层下方的衬底的中心区域相比，注入区域的电特性如此显着地改变，使植入区域的阈值电压升高到 约等于或大于中心区域中的基本均匀的阈值电压。

公开(公告)号：US20060003472A1

公开(公告)日：2006-01-05

申请号：US11215778

申请日：2005-08-30

申请人： Vishnu Agarwal ,  Howard Rhodes

发明人： Vishnu Agarwal ,  Howard Rhodes

IPC分类号： H01L21/00 ,  H01L29/76 ,  H01L21/8242

CPC分类号： H01L27/11502 ,  G11C11/22 ,  H01L27/11585 ,  H01L27/1159

摘要： Integrated memory circuits, key components in thousands of electronic and computer products, have been made using ferroelectric materials, which offer faster write cycles and lower power requirements than some other materials. However, the present inventors have recognized, for example, that conventional techniques for working with the polymers produce polymer layers with thickness variations that compromise performance and manufacturing yield. Accordingly, the present inventors devised unique methods and structures for polymer-based ferroelectric memories. One exemplary method entails forming an insulative layer on a substrate, forming two or more first conductive structures, with at least two of the first conductive structures separated by a gap, forming a gap-filling structure within the gap, and forming a polymer-based ferroelectric layer over the gap-filling structure and the first conductive structures. In some embodiments, the gap-filling structure is a polymer, a spin-on-glass, or a flow-fill oxide.

公开(公告)号：US07535047B2

公开(公告)日：2009-05-19

申请号：US10922582

申请日：2004-08-20

申请人： Vishnu Agarwal ,  Garry Anthony Mercaldi

发明人： Vishnu Agarwal ,  Garry Anthony Mercaldi

IPC分类号： H01L29/94

CPC分类号： H01L21/28202 ,  C23C8/02 ,  C23C16/56 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02222 ,  H01L21/02263 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28176 ,  H01L21/28238 ,  H01L21/3125 ,  H01L21/31612 ,  H01L29/513 ,  H01L29/518

摘要： An ultra thin dielectric film or dielectric layer on a semiconductor device is disclosed. In one embodiment, an oxide layer is formed over a substrate. A silicon-containing material is deposited over the oxide layer. The deposited material and oxide layer are processed in a plasma to form the dielectric layer or ultra thin dielectric film. The silicon-containing dielectric layer can allow for improved or smaller semiconductor devices. The silicon containing dielectric layer can be fabricated at low temperatures. Improved or smaller semiconductor devices may be accomplished by reducing leakage, increasing the dielectric constant or fabricating at lower temperatures.

摘要翻译： 公开了一种半导体器件上的超薄介电膜或电介质层。 在一个实施例中，在衬底上形成氧化物层。 在氧化物层上沉积含硅材料。 将沉积的材料和氧化物层在等离子体中进行处理以形成电介质层或超薄电介质膜。 含硅介电层可以允许改进或更小的半导体器件。 含硅介电层可以在低温下制造。 改进的或更小的半导体器件可以通过减少泄漏，增加介电常数或在较低温度下制造来实现。

公开(公告)号：US20050191948A1

公开(公告)日：2005-09-01

申请号：US11112104

申请日：2005-04-22

申请人： Vishnu Agarwal ,  Scott Meikle

发明人： Vishnu Agarwal ,  Scott Meikle

IPC分类号： B24B37/22 ,  B24B37/26 ,  B24D3/22 ,  B24D13/14 ,  B24B1/00

CPC分类号： B24B37/26 ,  B24B37/22 ,  B24D3/22 ,  Y10S977/776 ,  Y10S977/883 ,  Y10S977/888

摘要： Polishing pads used in the manufacturing of microelectronic devices, and apparatuses and methods for making and using such polishing pads. In one aspect of the invention, a polishing pad for planarizing microelectronic-device substrate assemblies has a backing member including a first surface and a second surface, a plurality of pattern elements distributed over the first surface of the backing member, and a hard cover layer over the pattern elements. The pattern elements define a plurality of contour surfaces projecting away from the first surface of the backing member. The cover layer at least substantially conforms to the contour surfaces of the pattern elements to form a plurality of hard nodules projecting away from the first surface of the backing member. The hard nodules define abrasive elements to contact and abrade material from a microelectronic-device substrate assembly. As such, the cover layer defines at least a portion of a planarizing surface of the polishing pad.

摘要翻译： 用于制造微电子器件的抛光垫，以及用于制造和使用这种抛光垫的装置和方法。 在本发明的一个方面，用于平坦化微电子器件衬底组件的抛光垫具有包括第一表面和第二表面的背衬构件，分布在衬垫构件的第一表面上的多个图案元件和硬覆盖层 超过图案元素。 图案元件限定远离背衬构件的第一表面突出的多个轮廓表面。 覆盖层至少基本上符合图案元件的轮廓表面，以形成多个突出远离背衬构件的第一表面的硬结节。 硬结节定义研磨元件以接触和研磨来自微电子器件衬底组件的材料。 因此，覆盖层限定抛光垫的平坦化表面的至少一部分。