-
1.发明授权Semiconductor interconnect and method of providing interconnect using a contact region 有权半导体互连和使用接触区提供互连的方法公开(公告)号：US06864582B1
公开(公告)日：2005-03-08
申请号：US10284761
申请日：2002-10-31
IPC分类号： H01L23/485 , H01L29/72
CPC分类号： H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor structure, interconnects between regions of a single device or different devices are achieved by forming contacts or plugs in thick oxide holes that span across the regions to be interconnected.
摘要翻译： 在半导体结构中，单个器件或不同器件的区域之间的互连通过在跨越待互连的区域的厚氧化物孔中形成接触或插塞来实现。
-
公开(公告)号：US07479435B1
公开(公告)日：2009-01-20
申请号：US11007565
申请日：2004-12-08
IPC分类号： H01L29/788
CPC分类号： H01L21/26586 , H01L21/2652 , H01L21/823418 , H01L27/088 , H01L29/0847
摘要： A MOS transistor and subsurface collectors can be formed by using a hard mask and precisely varying the implant angle, rotation, dose, and energy. In this case, a particular atomic species can be placed volumetrically in a required location under the hard mask. The dopant can be implanted to form sub-silicon volumes of arbitrary shapes, such as pipes, volumes, hemispheres, and interconnects.
摘要翻译： 可以通过使用硬掩模并精确地改变植入角度，旋转，剂量和能量来形成MOS晶体管和地下收集器。 在这种情况下，特定的原子物质可以体积地放置在硬掩模下的所需位置。 可以将掺杂剂注入以形成任意形状的子硅体积，例如管道，体积，半球和互连。
-
3.发明授权Method of forming a high-voltage silicon controlled rectifier structure with improved punch through resistance 有权形成具有改善的穿通电阻的高压可控硅整流器结构的方法公开(公告)号：US07238553B1
公开(公告)日：2007-07-03
申请号：US11134911
申请日：2005-05-23
IPC分类号： H01L21/332
CPC分类号： H01L27/0248 , H01L29/7436
摘要： When a high-voltage, such as from an ESD pulse, is placed across a silicon controlled rectifier, which includes an NPN transistor and a PNP transistor that is connected to the NPN transistor, the likelihood of punch through occurring between two regions of the rectifier is substantially reduced by forming the emitter of one transistor adjacent to the tails of the sinker down region of the other transistor.
摘要翻译： 当诸如ESD脉冲之类的高压被放置在包括NPN晶体管和连接到NPN晶体管的PNP晶体管的可控硅整流器上时，整流器的两个区域之间产生冲击的可能性 通过形成一个晶体管的发射极，与另一个晶体管的下沉区域的尾部相邻。
-
4.发明授权Vertical photodiode with heavily-doped regions of alternating conductivity types 有权具有交替导电类型的重掺杂区域的垂直光电二极管公开(公告)号：US07105373B1
公开(公告)日：2006-09-12
申请号：US10640963
申请日：2003-08-14
IPC分类号： H01L21/00
CPC分类号： H01L31/028 , H01L31/103 , Y02E10/547
摘要： A single junction interdigitated photodiode utilizes a stack of alternating highly doped first regions of a first conductivity type and highly doped second regions of a second conductivity type, which are formed below and contact the first regions, to collect photons. In addition, a highly doped sinker of a first conductivity type contacts each first region, and a highly doped sinker of a second conductivity type contacts each second region.
摘要翻译： 单结交叉光电二极管利用第一导电类型的交替的高度掺杂的第一区域和第二导电类型的高度掺杂的第二区域的堆叠，其在下面形成并接触第一区域以收集光子。 此外，第一导电类型的高掺杂沉降片接触每个第一区域，并且第二导电类型的高掺杂沉降片接触每个第二区域。
-
5.发明授权High-voltage silicon controlled rectifier structure with improved punch through resistance 有权高压可控硅整流器结构，具有改善的穿通电阻公开(公告)号：US06919588B1
公开(公告)日：2005-07-19
申请号：US10650000
申请日：2003-08-27
CPC分类号： H01L27/0248 , H01L29/7436
摘要： When a high-voltage, such as from an ESD pulse, is placed across a silicon controlled rectifier, which includes an NPN transistor and a PNP transistor that is connected to the NPN transistor, the likelihood of punch through occurring between two regions of the rectifier is substantially reduced by forming the emitter of one transistor adjacent to the tails of the sinker down region of the other transistor.
摘要翻译： 当诸如ESD脉冲之类的高压被放置在包括NPN晶体管和连接到NPN晶体管的PNP晶体管的可控硅整流器上时，整流器的两个区域之间产生冲击的可能性 通过形成一个晶体管的发射极，与另一个晶体管的下沉区域的尾部相邻。
-
6.发明授权公开(公告)号：US07192857B1
公开(公告)日：2007-03-20
申请号：US11109961
申请日：2005-04-20
IPC分类号： H01L21/3205
CPC分类号： H01L29/41758 , H01L23/4824 , H01L29/0692 , H01L29/41725 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： A power transistor structure uses metal drain and source strips with non-uniform widths to reduce variations in current density across the power transistor structure. The reductions in current density, in turn, reduce the source-to-drain turn on resistance and maximize the overall current carrying capacity of power transistor structure.
摘要翻译： 功率晶体管结构使用具有不均匀宽度的金属漏极和源极条来减小跨越功率晶体管结构的电流密度的变化。 电流密度的降低又降低了源极到漏极导通电阻，并使功率晶体管结构的总载流能力最大化。
-
公开(公告)号：US06933562B1
公开(公告)日：2005-08-23
申请号：US10609191
申请日：2003-06-27
IPC分类号： H01L23/482 , H01L29/06 , H01L29/417 , H01L29/78 , H01L29/94 , H01L31/113 , H01L31/119 , H01L29/46 , H01L31/62
CPC分类号： H01L29/41758 , H01L23/4824 , H01L29/0692 , H01L29/41725 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： A power transistor structure uses metal drain and source strips with non-uniform widths to reduce variations in current density across the power transistor structure. The reductions in current density, in turn, reduce the source-to-drain turn on resistance and maximize the overall current carrying capacity of power transistor structure.
摘要翻译： 功率晶体管结构使用具有不均匀宽度的金属漏极和源极条来减小跨越功率晶体管结构的电流密度的变化。 电流密度的降低又降低了源极到漏极导通电阻，并使功率晶体管结构的总载流能力最大化。
-
公开(公告)号：US07037814B1
公开(公告)日：2006-05-02
申请号：US10683858
申请日：2003-10-10
CPC分类号： H01L22/14 , H01L21/26513
摘要： In an integrated circuit, dopant concentration levels are adjusted by making use of a perforated mask. Doping levels for different regions across an integrated circuit can be differently defined by making use of varying size and spacings to the perforations in the mask. The diffusion of dopant is completed by making use of an annealing stage.
摘要翻译： 在集成电路中，通过使用穿孔掩模来调整掺杂剂浓度水平。 跨越集成电路的不同区域的掺杂水平可以通过利用面罩中的穿孔的不同尺寸和间距而不同地限定。 通过使用退火阶段完成掺杂剂的扩散。
-
公开(公告)号：US06844585B1
公开(公告)日：2005-01-18
申请号：US10173911
申请日：2002-06-17
IPC分类号： H01L21/265 , H01L21/8234 , H01L27/088 , H01L29/08 , H01L29/788
CPC分类号： H01L21/26586 , H01L21/2652 , H01L21/823418 , H01L27/088 , H01L29/0847
摘要： A MOS transistor and subsurface collectors can be formed by using a hard mask and precisely varying the implant angle, rotation, dose, and energy. In this case, a particular atomic species can be placed volumetrically in a required location under the hard mask. The dopant can be implanted to form sub-silicon volumes of arbitrary shapes, such as pipes, volumes, hemispheres, and interconnects.
摘要翻译： 可以通过使用硬掩模并精确地改变植入角度，旋转，剂量和能量来形成MOS晶体管和地下收集器。 在这种情况下，特定的原子物质可以体积地放置在硬掩模下的所需位置。 可以将掺杂剂注入以形成任意形状的子硅体积，例如管道，体积，半球和互连。
-
10.发明授权公开(公告)号：US06707117B1
公开(公告)日：2004-03-16
申请号：US10285235
申请日：2002-10-31
IPC分类号： H01C2976
CPC分类号： H01L21/28518 , H01L21/76889 , H01L21/76895 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor structure, interconnects between regions of a single device or different devices are achieved by forming metal plugs that span across the regions to be interconnected, wherein the plugs are formed from the metal used in forming a silicide layer on the structure. The metal is masked off in desired areas prior to etching, to leave the metal plugs.
摘要翻译： 在半导体结构中，单个器件或不同器件的区域之间的互连通过形成跨越要互连的区域的金属插塞来实现，其中插塞由在结构上形成硅化物层所用的金属形成。 在蚀刻之前，将金属掩盖在所需区域中，以留下金属塞。
-
-
-
-
-
-
-
-
-
搜索结果
282 条记录 (耗时 0.025 秒)
