公开(公告)号：US20160049419A1

公开(公告)日：2016-02-18

申请号：US14920223

申请日：2015-10-22

申请人： WOOKHYOUNG LEE ,  Jongsik CHUN ,  SUNIL SHIM ,  Jaeyoung AHN ,  JUYUL LEE ,  KIHYUN HWANG ,  HANSOO KIM ,  WOONKYUNG LEE ,  JAEHOON JANG ,  WONSEOK CHO

发明人： WOOKHYOUNG LEE ,  Jongsik CHUN ,  SUNIL SHIM ,  Jaeyoung AHN ,  JUYUL LEE ,  KIHYUN HWANG ,  HANSOO KIM ,  WOONKYUNG LEE ,  JAEHOON JANG ,  WONSEOK CHO

IPC分类号： H01L27/115

CPC分类号： H01L27/11565 ,  G11C5/06 ,  G11C5/063 ,  G11C7/00 ,  G11C7/18 ,  H01L23/48 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a semiconductor device including gate structures provided on a substrate, a separation insulating layer interposed between the gate structures, and a plurality of cell pillars connected to the substrate through each gate structure. Each gate structure may include horizontal electrodes vertically stacked on the substrate, and an interval between adjacent ones of the cell pillars is non-uniform.

摘要翻译： 提供了一种半导体器件，其包括设置在基板上的栅极结构，插入在栅极结构之间的分离绝缘层以及通过每个栅极结构连接到基板的多个单元柱。 每个栅极结构可以包括垂直堆叠在基板上的水平电极，并且相邻的单元柱之间的间隔是不均匀的。

公开(公告)号：US20130270643A1

公开(公告)日：2013-10-17

申请号：US13796118

申请日：2013-03-12

申请人： JUYUL LEE ,  BUMSU KIM ,  KWANGMIN PARK ,  HYUN PARK ,  JAE-YOUNG AHN ,  DONGCHUL YOO ,  JONGSIK CHUN ,  KIHYUN HWANG

发明人： JUYUL LEE ,  BUMSU KIM ,  KWANGMIN PARK ,  HYUN PARK ,  JAE-YOUNG AHN ,  DONGCHUL YOO ,  JONGSIK CHUN ,  KIHYUN HWANG

IPC分类号： H01L27/105

CPC分类号： H01L27/11582 ,  H01L27/1052 ,  H01L29/7926

摘要： A three-dimensional (3D) semiconductor memory device includes an electrode separation pattern, a stack structure, a data storage layer, and a channel structure. The electrode separation pattern is disposed on a substrate. A stack structure is disposed on a sidewall of the electrode separation pattern. The stack structure includes a corrugated sidewall opposite to the sidewall of the electrode separation pattern. The sidewall of the electrode separation pattern is vertical to the substrate. A data storage layer is disposed on the corrugated sidewall. A channel structure is disposed on the charge storage layer.

公开(公告)号：US20150145020A1

公开(公告)日：2015-05-28

申请号：US14510532

申请日：2014-10-09

申请人： CHAEHO KIM ,  KIHYUN HWANG ,  DONGWOO KIM ,  WOONG LEE ,  JUNGGEUN JEE

发明人： CHAEHO KIM ,  KIHYUN HWANG ,  DONGWOO KIM ,  WOONG LEE ,  JUNGGEUN JEE

IPC分类号： H01L27/115 ,  H01L29/66 ,  H01L21/02

CPC分类号： H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

摘要： A method of fabricating a three-dimensional (3D) semiconductor memory device is provided. Sacrificial layers and insulating layers are alternately and repeatedly stacked on a top surface of a substrate to form a thin layer structure. A channel structure penetrating the thin layer structure is formed to be in contact with the substrate. A trench penetrating the thin layer structure is formed. The sacrificial layers, the insulating layers and the substrate are exposed in the trench. A recess region formed in the substrate exposed by the trench. A semiconductor pattern filling is formed the recess region. The sacrificial layers exposed by the trench are replaced with gate patterns.

摘要翻译： 提供一种制造三维（3D）半导体存储器件的方法。 牺牲层和绝缘层交替重复堆叠在基板的顶表面上以形成薄层结构。 穿透薄层结构的沟道结构形成为与衬底接触。 形成穿透薄层结构的沟槽。 牺牲层，绝缘层和衬底暴露在沟槽中。 形成在衬底中的由沟槽暴露的凹陷区域。 半导体图案填充形成为凹部。 由沟槽暴露的牺牲层被栅极图案替代。

公开(公告)号：US20170294445A1

公开(公告)日：2017-10-12

申请号：US15467311

申请日：2017-03-23

申请人： YONG-HOON SON ,  HANMEI CHOI ,  KIHYUN HWANG

发明人： YONG-HOON SON ,  HANMEI CHOI ,  KIHYUN HWANG

IPC分类号： H01L27/11582 ,  H01L27/1157

CPC分类号： H04L5/0091 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7926 ,  H04L1/1812

摘要： A non-volatile memory structure can include a substrate extending horizontally and a filling insulating pattern extending vertically from the substrate. A plurality of active channel patterns can extend vertically from the substrate in a zig-zag pattern around a perimeter of the filling insulating pattern, where each of the active channel patterns having a respective non-circular shaped horizontal cross-section. A vertical stack of a plurality of gate lines can each extend horizontally around the filling insulating pattern and the plurality of active channel patterns.