公开(公告)号：US10685972B2

公开(公告)日：2020-06-16

申请号：US15514239

申请日：2014-09-26

申请人： Sunggil Kim ,  Phil Ouk Nam ,  Gukhyon Yon ,  Sunghae Lee ,  Woojin Jang ,  Dongchul Yoo ,  Hunhyeong Lim ,  Junggeun Jee ,  Kihyun Hwang

发明人： Sunggil Kim ,  Phil Ouk Nam ,  Gukhyon Yon ,  Sunghae Lee ,  Woojin Jang ,  Dongchul Yoo ,  Hunhyeong Lim ,  Junggeun Jee ,  Kihyun Hwang

IPC分类号： H01L27/11582 ,  H01L27/11568 ,  H01L21/28 ,  H01L27/115 ,  H01L49/02 ,  H01L21/02 ,  H01L21/311 ,  H01L27/1157 ,  H01L29/10

摘要： The inventive concepts provide semiconductor memory devices and methods for fabricating the same. The semiconductor memory device may include a plurality of gates vertically stacked on a substrate, a vertical channel filling a channel hole vertically penetrating the plurality of gates, and a memory layer vertically extending on an inner sidewall of the channel. The vertical channel may include a lower channel filling a lower region of the channel hole and electrically connected to the substrate, and an upper channel filling an upper region of the channel hole and contacting the lower channel. The upper channel may extend along the memory layer and the lower channel in the upper region of the channel hole and may have a uniform thickness.

公开(公告)号：US20150333084A1

公开(公告)日：2015-11-19

申请号：US14810845

申请日：2015-07-28

申请人： Yong-Hoon Son ,  Jung Ho Kim ,  Seungjae Baik ,  Myoungbum Lee ,  Kihyun Hwang

发明人： Yong-Hoon Son ,  Jung Ho Kim ,  Seungjae Baik ,  Myoungbum Lee ,  Kihyun Hwang

IPC分类号： H01L27/115

CPC分类号： H01L27/11551 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582

摘要： Nonvolatile memory devices include a string of nonvolatile memory cells on a substrate. This string of nonvolatile memory cells includes a first vertical stack of nonvolatile memory cells on the substrate and a string selection transistor on the first vertical stack of nonvolatile memory cells. A second vertical stack of nonvolatile memory cells is also provided on the substrate and a ground selection transistor is provided on the second vertical stack of nonvolatile memory cells. This second vertical stack of nonvolatile memory cells is provided adjacent the first vertical stack of nonvolatile memory cells. A conjunction doped semiconductor region is provided in the substrate. This conjunction doped region electrically connects the first vertical stack of nonvolatile memory cells in series with the second vertical stack of nonvolatile memory cells so that these stacks can operate as a single NAND-type string of memory cells.

摘要翻译： 非易失性存储器件包括在衬底上的一串非易失性存储器单元。 这一串非易失性存储单元包括衬底上的非易失性存储单元的第一垂直堆叠和非易失性存储单元的第一垂直堆叠上的串选择晶体管。 第二垂直堆叠的非易失性存储单元也设置在衬底上，并且在非易失性存储单元的第二垂直堆叠上提供接地选择晶体管。 非易失性存储单元的第二垂直堆叠被提供为与非易失性存储单元的第一垂直堆叠相邻。 在衬底中提供连接掺杂半导体区域。 该连接掺杂区域将非易失性存储器单元的第一垂直堆叠与第二垂直堆叠的非易失性存储器单元电连接，使得这些堆叠可以作为单个NAND型存储器单元串工作。

公开(公告)号：US20150145020A1

公开(公告)日：2015-05-28

申请号：US14510532

申请日：2014-10-09

申请人： CHAEHO KIM ,  KIHYUN HWANG ,  DONGWOO KIM ,  WOONG LEE ,  JUNGGEUN JEE

发明人： CHAEHO KIM ,  KIHYUN HWANG ,  DONGWOO KIM ,  WOONG LEE ,  JUNGGEUN JEE

IPC分类号： H01L27/115 ,  H01L29/66 ,  H01L21/02

CPC分类号： H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

摘要： A method of fabricating a three-dimensional (3D) semiconductor memory device is provided. Sacrificial layers and insulating layers are alternately and repeatedly stacked on a top surface of a substrate to form a thin layer structure. A channel structure penetrating the thin layer structure is formed to be in contact with the substrate. A trench penetrating the thin layer structure is formed. The sacrificial layers, the insulating layers and the substrate are exposed in the trench. A recess region formed in the substrate exposed by the trench. A semiconductor pattern filling is formed the recess region. The sacrificial layers exposed by the trench are replaced with gate patterns.

摘要翻译： 提供一种制造三维（3D）半导体存储器件的方法。 牺牲层和绝缘层交替重复堆叠在基板的顶表面上以形成薄层结构。 穿透薄层结构的沟道结构形成为与衬底接触。 形成穿透薄层结构的沟槽。 牺牲层，绝缘层和衬底暴露在沟槽中。 形成在衬底中的由沟槽暴露的凹陷区域。 半导体图案填充形成为凹部。 由沟槽暴露的牺牲层被栅极图案替代。

公开(公告)号：US20150145018A1

公开(公告)日：2015-05-28

申请号：US14568737

申请日：2014-12-12

申请人： Jeeyong Kim ,  Woonkyung Lee ,  Sunggil Kim ,  Jin-Kyu Kang ,  Jung-Hwan Lee ,  Bonyoung Koo ,  Kihyun Hwang ,  Byoungsun Ju ,  Jintae Noh

发明人： Jeeyong Kim ,  Woonkyung Lee ,  Sunggil Kim ,  Jin-Kyu Kang ,  Jung-Hwan Lee ,  Bonyoung Koo ,  Kihyun Hwang ,  Byoungsun Ju ,  Jintae Noh

IPC分类号： H01L29/49 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11526 ,  H01L21/28 ,  H01L21/76841 ,  H01L23/48 ,  H01L23/535 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/4958 ,  H01L29/78 ,  H01L29/788 ,  H01L29/7883 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration.

摘要翻译： 提供半导体器件和制造半导体器件的方法。 半导体器件包括形成在衬底上的电荷存储图案; 形成在电荷存储图案上的电介质图案; 第一导电图案，包括掺杂有第一浓度的第一杂质的硅，所述第一导电图案设置在所述电介质图案上; 以及第二导电图案，其包括掺杂有第二浓度的第二杂质的金属硅化物，所述第二导电图案设置在所述第一导电图案上。 第一浓度可能高于第二浓度。

公开(公告)号：US08575682B2

公开(公告)日：2013-11-05

申请号：US13323452

申请日：2011-12-12

申请人： Bio Kim ,  Kihyun Hwang ,  Jaeyoung Ahn ,  SeungHyun Lim ,  Dongwoo Kim

发明人： Bio Kim ,  Kihyun Hwang ,  Jaeyoung Ahn ,  SeungHyun Lim ,  Dongwoo Kim

IPC分类号： H01L29/66

CPC分类号： H01L29/66666 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

摘要： Provided are three-dimensional semiconductor memory devices and methods of forming the same. The device includes a substrate, conductive patterns stacked on the substrate, and an active pattern penetrating the conductive patterns to be connected to the substrate. The active pattern may include a first doped region provided in an upper portion of the active pattern, and a diffusion-resistant doped region overlapped with at least a portion of the first doped region. The diffusion-resistant doped region may be a region doped with carbon.

摘要翻译： 提供三维半导体存储器件及其形成方法。 该器件包括衬底，堆叠在衬底上的导电图案，以及穿透要连接到衬底的导电图案的有源图案。 有源图案可以包括设置在有源图案的上部的第一掺杂区域和与第一掺杂区域的至少一部分重叠的扩散阻抗掺杂区域。 扩散阻止掺杂区域可以是掺杂有碳的区域。

公开(公告)号：US08507918B2

公开(公告)日：2013-08-13

申请号：US13018833

申请日：2011-02-01

申请人： Yong-Hoon Son ,  Myoungbum Lee ,  Kihyun Hwang

发明人： Yong-Hoon Son ,  Myoungbum Lee ,  Kihyun Hwang

IPC分类号： H01L29/04

CPC分类号： H01L27/11582

摘要： Memory devices include a stack of interleaved conductive patterns and insulating patterns disposed on a substrate. A semiconductor pattern passes through the stack of conductive patterns and insulating patterns to contact the substrate, the semiconductor pattern having a graded grain size distribution wherein a mean grain size in a first portion of the semiconductor pattern proximate the substrate is less than a mean grain size in a second portion of the semiconductor pattern further removed from the substrate. The graded grain size distribution may be achieved, for example, by partial laser annealing.

摘要翻译： 存储器件包括布置在衬底上的交错导电图案和绝缘图案的堆叠。 半导体图形通过导体图案和绝缘图案堆叠以接触衬底，半导体图案具有渐变的晶粒尺寸分布，其中半导体图案的靠近衬底的第一部分中的平均晶粒尺寸小于平均晶粒尺寸 在从衬底进一步去除的半导体图案的第二部分中。 分级粒度分布可以通过例如部分激光退火来实现。

公开(公告)号：US08232590B2

公开(公告)日：2012-07-31

申请号：US12829689

申请日：2010-07-02

申请人： Byoungsun Ju ,  Sunggil Kim ,  Jintae Noh ,  Siyoung Choi ,  Kihyun Hwang

发明人： Byoungsun Ju ,  Sunggil Kim ,  Jintae Noh ,  Siyoung Choi ,  Kihyun Hwang

IPC分类号： H01L29/788

CPC分类号： H01L29/7883 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/4916 ,  H01L29/66825

摘要： Provided is a nonvolatile memory device. The nonvolatile memory device includes: a tunnel insulation layer on a semiconductor substrate; a floating gate electrode including a bottom gate electrode doped with carbon and contacting the tunnel insulation layer and a top gate electrode on the bottom gate electrode; a gate interlayer insulation layer on the floating gate electrode; and a control gate electrode on the gate interlayer insulation layer.

摘要翻译： 提供了一种非易失性存储器件。 非易失性存储器件包括：半导体衬底上的隧道绝缘层; 包括掺杂有碳并与隧道绝缘层接触的底栅电极和底栅电极上的顶栅电极的浮栅电极; 浮栅电极上的栅极层间绝缘层; 以及栅极层间绝缘层上的控制栅电极。

公开(公告)号：US20120153372A1

公开(公告)日：2012-06-21

申请号：US13323452

申请日：2011-12-12

申请人： Bio Kim ,  Kihyun Hwang ,  Jaeyoung Ahn ,  SeungHyun Lim ,  Dongwoo Kim

发明人： Bio Kim ,  Kihyun Hwang ,  Jaeyoung Ahn ,  SeungHyun Lim ,  Dongwoo Kim

IPC分类号： H01L29/78

CPC分类号： H01L29/66666 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

摘要： Provided are three-dimensional semiconductor memory devices and methods of forming the same. The device includes a substrate, conductive patterns stacked on the substrate, and an active pattern penetrating the conductive patterns to be connected to the substrate. The active pattern may include a first doped region provided in an upper portion of the active pattern, and a diffusion-resistant doped region overlapped with at least a portion of the first doped region. The diffusion-resistant doped region may be a region doped with carbon.

摘要翻译： 提供三维半导体存储器件及其形成方法。 该器件包括衬底，堆叠在衬底上的导电图案，以及穿透要连接到衬底的导电图案的有源图案。 有源图案可以包括设置在有源图案的上部的第一掺杂区域和与第一掺杂区域的至少一部分重叠的扩散阻抗掺杂区域。 扩散阻止掺杂区域可以是掺杂有碳的区域。

公开(公告)号：US20110303971A1

公开(公告)日：2011-12-15

申请号：US13157659

申请日：2011-06-10

申请人： Changwon Lee ,  Kihyun Hwang ,  Hanmei Choi ,  Sun Woo Lee ,  Junkyu Yang ,  Sunggil Kim ,  Jeonggil Lee ,  Seon-Ho Jo

发明人： Changwon Lee ,  Kihyun Hwang ,  Hanmei Choi ,  Sun Woo Lee ,  Junkyu Yang ,  Sunggil Kim ,  Jeonggil Lee ,  Seon-Ho Jo

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

摘要： A method for manufacturing a three-dimensional semiconductor memory includes forming a plurality of stacked structures disposed on a substrate to be spaced apart from each other, each of the stacked structures including a plurality of dielectric patterns and a plurality of polysilicon patterns alternately stacked, forming a metal layer to cover sidewalls of the stacked structures and a top surface of the substrate exposed between the stacked structures, and forming stacked gate electrodes on the substrate and a conductive line in the substrate by performing a silicidation process between the metal layer and each of the polysilicon patterns and the substrate.

摘要翻译： 一种三维半导体存储器的制造方法，其特征在于，在基板上形成多个层叠结构，使其彼此间隔开，所述堆叠结构中的每一个包括多个电介质图案和多个多晶硅图案，交替层叠，形成 覆盖层叠结构的侧壁的金属层和露出在层叠结构之间的基板的顶面，通过在金属层与金属层之间进行硅化处理，在基板上形成层叠的栅电极和基板的导电线 多晶硅图案和衬底。

公开(公告)号：US20110207303A1

公开(公告)日：2011-08-25

申请号：US13030454

申请日：2011-02-18

申请人： Jin Ha Jeong ,  Jung Ho Kim ,  Kihyun Hwang ,  Yong-Hoon Son

发明人： Jin Ha Jeong ,  Jung Ho Kim ,  Kihyun Hwang ,  Yong-Hoon Son

IPC分类号： H01L21/368

CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/42352 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7827 ,  H01L29/7926

摘要： Methods for fabricating a semiconductor device are provided. In the methods, first material layers and second material layers may be alternatingly and repeatedly stacked on a substrate. An opening penetrating the first material layers and the second material layers may be formed. A semiconductor solution may be formed in the opening by using a spin-on process.

摘要翻译： 提供了制造半导体器件的方法。 在这些方法中，第一材料层和第二材料层可以交替地和重复堆叠在基底上。 可以形成贯穿第一材料层和第二材料层的开口。 可以通过使用旋涂工艺在开口中形成半导体溶液。