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    Methods of fabricating three-dimensional semiconductor memory devices
    6.
    发明授权
    Methods of fabricating three-dimensional semiconductor memory devices 有权
    制造三维半导体存储器件的方法

    公开(公告)号：US09397114B2

    公开(公告)日：2016-07-19

    申请号：US13475023

    申请日：2012-05-18

    申请人： Jumi Yun ,  Kwangmin Park ,  Dongchul Yoo ,  Byong-hyun Jang

    发明人： Jumi Yun ,  Kwangmin Park ,  Dongchul Yoo ,  Byong-hyun Jang

    IPC分类号： H01L27/00 ,  H01L21/00 ,  H01L27/115 ,  H01L21/31 ,  H01L29/792

    CPC分类号： H01L27/11582 ,  H01L21/31 ,  H01L29/7926

    摘要： Methods of fabricating three-dimensional semiconductor memory devices including forming a plate stack structure with insulating layers and sacrificial layers stacked alternatingly on a substrate, forming first and second trenches separating the plate stack structure into a plurality of mold structures, the first trench being between the second trenches, forming first vertical insulating separators in the first and second trenches, forming semiconductor patterns penetrating the mold structure and being spaced apart from the first and second trenches, removing the first vertical insulating separator from the second trench to expose the sacrificial layers, removing the sacrificial layers exposed by the second trench to form recess regions partially exposing the semiconductor patterns and the first vertical insulating separator, and forming conductive patterns in the recess regions.

    摘要翻译： 制造三维半导体存储器件的方法包括：将具有绝缘层和牺牲层的叠层结构形成在衬底上的层叠层，形成将板堆结构分成多个模具结构的第一和第二沟槽，第一沟槽位于 第二沟槽，在第一和第二沟槽中形成第一垂直绝缘隔板，形成穿透模具结构并与第一和第二沟槽隔开的半导体图案，从第二沟槽移除第一垂直绝缘隔板以暴露牺牲层，去除 所述牺牲层由所述第二沟槽暴露以形成部分地暴露所述半导体图案和所述第一垂直绝缘隔板的凹部区域，以及在所述凹部区域中形成导电图案。

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    7.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20160049423A1

    公开(公告)日：2016-02-18

    申请号：US14695249

    申请日：2015-04-24

    申请人： Dongchul YOO ,  Chaeho KIM ,  Jaeyoung AHN ,  Woong LEE

    发明人： Dongchul YOO ,  Chaeho KIM ,  Jaeyoung AHN ,  Woong LEE

    IPC分类号： H01L27/115

    CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

    摘要： A three-dimensional semiconductor device may include a substrate including a cell array region, a word line contact region, and a peripheral circuit region, gate electrodes stacked on the substrate to extend from the cell array region to the word line contact region, a channel hole penetrating the gate electrodes on the cell array region and exposing an active region of the substrate, a dummy hole penetrating the gate electrodes on the word line contact region and exposing a device isolation layer provided on the substrate, and a semiconductor pattern provided in the channel hole but not in the dummy hole.

    摘要翻译： 三维半导体器件可以包括包括单元阵列区域，字线接触区域和外围电路区域的基板，堆叠在基板上以从单元阵列区域延伸到字线接触区域的栅电极，通道 穿透单元阵列区域上的栅电极并暴露基板的有源区域，穿过字线接触区域上的栅电极的裸孔，并暴露设置在基板上的器件隔离层，以及设置在基极上的半导体图案 通道孔，但不在虚拟孔中。

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    10.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20150279857A1

    公开(公告)日：2015-10-01

    申请号：US14539140

    申请日：2014-11-12

    申请人： Jung-Hwan KIM ,  Hanvit YANG ,  Jintae NOH ,  Dongchul YOO

    发明人： Jung-Hwan KIM ,  Hanvit YANG ,  Jintae NOH ,  Dongchul YOO

    IPC分类号： H01L27/115 ,  H01L23/00

    CPC分类号： H01L27/11582

    摘要： Inventive concepts provide semiconductor memory devices and methods of fabricating the same. A stack structure and vertical channel structures are provided on a substrate. The stack structure includes insulating layers and gate electrodes alternately and repeatedly stacked on the substrate. A first vertical channel pattern is disposed in a lower portion of each vertical channel structure. A gate oxide layer is formed on a sidewall of the first vertical channel pattern. A recess region is formed in the substrate between the vertical channel structures. A buffer oxide layer is formed in the recess region. An oxidation inhibiting layer is provided in the substrate to surround the recess region. The oxidation inhibiting layer is in contact with the buffer oxide layer and inhibits growth of the buffer oxide layer.

    摘要翻译： 本发明的概念提供半导体存储器件及其制造方法。 堆叠结构和垂直通道结构设置在基板上。 堆叠结构包括在基板上交替重复堆叠的绝缘层和栅电极。 第一垂直通道图案设置在每个垂直通道结构的下部。 栅极氧化层形成在第一垂直沟道图案的侧壁上。 在垂直通道结构之间的衬底中形成凹陷区域。 在凹陷区域中形成缓冲氧化物层。 在基板中设置氧化抑制层以包围凹部。 氧化抑制层与缓冲氧化物层接触并抑制缓冲氧化物层的生长。