公开(公告)号：US20060249799A1

公开(公告)日：2006-11-09

申请号：US11481120

申请日：2006-07-05

申请人： Wagdi Abadeer ,  Jeffrey Brown ,  David Fried ,  Robert Gauther ,  Edward Nowak ,  Jed Rankio ,  William Tonti

发明人： Wagdi Abadeer ,  Jeffrey Brown ,  David Fried ,  Robert Gauther ,  Edward Nowak ,  Jed Rankio ,  William Tonti

IPC分类号： H01L29/76

CPC分类号： H01L29/786 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/4908 ,  H01L29/78615

摘要： An integrated circuit chip and a semiconductor structure. The integrated circuit chip includes: a thick-body device containing a semiconductor mesa and a doped body contact; and a field effect transistor on a first sidewall of a semiconductor mesa, wherein the doped body contact is on a second sidewall of the semiconductor mesa, and wherein the semiconductor mesa is disposed between the field effect transistor and the doped body contact. The semiconductor structure includes: a buried oxide layer on a semiconductor wafer; a thin fin structure on the buried oxide layer, wherein the thin fin structure includes a first hard mask on a semiconductor fin, wherein the semiconductor fin is disposed between the first hard mask and a surface of the buried oxide layer; and a thick mesa structure on the buried oxide layer, and wherein the thick mesa structure includes a semiconductor mesa.

公开(公告)号：US20070254438A1

公开(公告)日：2007-11-01

申请号：US11774663

申请日：2007-07-09

申请人： Andres Bryant ,  Meikei Ieong ,  K. Muller ,  Edward Nowak ,  David Fried ,  Jed Rankin

发明人： Andres Bryant ,  Meikei Ieong ,  K. Muller ,  Edward Nowak ,  David Fried ,  Jed Rankin

IPC分类号： H01L21/336

CPC分类号： H01L29/4908 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/66795 ,  H01L29/785

摘要： A method for forming a transistor. A semiconductor substrate is provided. The semiconductor substrate is patterned to provide a first body edge. A first gate structure of a first fermi level is provided adjacent the first body edge. The semiconductor substrate is patterned to provide a second body edge. The first and second body edges of the semiconductor substrate define a transistor body. A second gate structure of a second fermi level is provided adjacent the second body edge. A substantially uniform dopant concentration density is formed throughout the transistor body.

摘要翻译： 一种形成晶体管的方法。 提供半导体衬底。 图案化半导体衬底以提供第一本体边缘。 在第一身体边缘附近提供第一费米能级的第一门结构。 图案化半导体衬底以提供第二本体边缘。 半导体衬底的第一和第二主体边缘限定晶体管体。 在第二身体边缘附近设置第二费米能级的第二门结构。 在整个晶体管本体中形成基本均匀的掺杂剂浓度密度。

公开(公告)号：US20060154423A1

公开(公告)日：2006-07-13

申请号：US10538911

申请日：2002-12-19

申请人： David Fried ,  Edward Nowak ,  Beth Rainey

发明人： David Fried ,  Edward Nowak ,  Beth Rainey

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： Methods for forming a spacer (44) for a first structure (24, 124), such as a gate structure of a FinFET, and at most a portion of a second structure (14), such as a fin, without detrimentally altering the second structure. The methods generate a first structure (24) having a top portion (30, 130) that overhangs an electrically conductive lower portion (32, 132) and a spacer (44) under the overhang (40, 140). The overhang (40, 140) may be removed after spacer processing. Relative to a FinFET, the overhang protects parts of the fin (14) such as regions adjacent and under the gate structure (24, 124), and allows for exposing sidewalls of the fin (14) to other processing such as selective silicon growth and implantation. As a result, the methods allow sizing of the fin (14) and construction of the gate structure (24, 124) and spacer without detrimentally altering (e.g., eroding by forming a spacer thereon) the fin (14) during spacer processing. A FinFET (100) including a gate structure (24, 124) and spacer (44) is also disclosed.

摘要翻译： 用于形成用于第一结构（24,124）的间隔物（44）的方法，诸如FinFET的栅极结构，以及至少一部分第二结构（14）的一部分，例如翅片，而不会有害地改变第二结构 结构体。 该方法产生第一结构（24），该第一结构（24）具有突出在导电下部（32,132）之下的顶部（30,130）和在突出部（40,140）下方的间隔物（44）。 间隔物处理后，可以移除悬垂物（40,140）。 相对于FinFET，突出端保护翅片（14）的部分，例如在栅极结构（24,124）附近和下方的区域，并且允许将鳍片（14）的侧壁暴露于诸如选择性硅生长的其它处理，以及 植入。 结果，这些方法允许翅片（14）的尺寸和栅极结构（24,124）和间隔物的结构，而不会在间隔物处理期间有害地改变（例如，通过在其上形成隔离物的侵蚀）翅片（14）。 还公开了包括栅极结构（24,124）和间隔物（44）的FinFET（100）。

公开(公告)号：US20060038216A1

公开(公告)日：2006-02-23

申请号：US11216862

申请日：2005-08-31

申请人： David Fried ,  Edward Nowak

发明人： David Fried ,  Edward Nowak

IPC分类号： H01L29/94

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L28/90 ,  H01L29/785

摘要： Device designs and methods are described for incorporating capacitors commonly used in planar CMOS technology into a FinFET based technology. A capacitor includes at least one single-crystal Fin structure having a top surface and a first side surface opposite a second side surface. Adjacent the top surface of the at least one Fin structure is at least one insulator structure. Adjacent the at least one insulator structure and over a portion of the at least one Fin structure is at least one conductor structure. Decoupling capacitors may be formed at the circuit device level using simple design changes within the same integration method, thereby allowing any number, combination, and/or type of decoupling capacitors to be fabricated easily along with other devices on the same substrate to provide effective decoupling capacitance in an area-efficient manner with superior high-frequency response.

公开(公告)号：US20050121676A1

公开(公告)日：2005-06-09

申请号：US10987532

申请日：2004-11-12

申请人： David Fried ,  Randy Mann ,  K. Muller ,  Edward Nowak

发明人： David Fried ,  Randy Mann ,  K. Muller ,  Edward Nowak

IPC分类号： H01L21/8244 ,  H01L21/84 ,  H01L27/12 ,  H01L29/76

CPC分类号： H01L27/11 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/785 ,  Y10S257/903

摘要： The present invention provides a device design and method for forming the same that results in Fin Field Effect Transistors having different gains without negatively impacting device density. The present invention forms relatively low gain FinFET transistors in a low carrier mobility plane and relatively high gain FinFET transistors in a high carrier mobility plane. Thus formed, the FinFETs formed in the high mobility plane have a relatively higher gain than the FinFETs formed in the low mobility plane. The embodiments are of particular application to the design and fabrication of a Static Random Access Memory (SRAM) cell. In this application, the bodies of the n-type FinFETs used as transfer devices are formed along the {110} plane. The bodies of the n-type FinFETs and p-type FinFETs used as the storage latch are formed along the {100}. Thus formed, the transfer devices will have a gain approximately half that of the n-type storage latch devices, facilitating proper SRAM operation

摘要翻译： 本发明提供了一种用于形成它的器件设计和方法，其导致Fin场效应晶体管具有不同的增益而不会不利地影响器件密度。 本发明在低载流子迁移率平面中形成相对较低的增益FinFET晶体管，并在高载流子迁移率平面内形成相对较高的增益FinFET晶体管。 如此形成的，在高迁移率平面中形成的FinFET具有比在低迁移率平面中形成的FinFET更高的增益。 这些实施例特别适用于静态随机存取存储器（SRAM）单元的设计和制造。 在这种应用中，用作转移装置的n型FinFET的主体沿{110}平面形成。 用作存储锁存器的n型FinFET和p型FinFET的主体沿{100}形成。 如此形成的，传送装置的增益大约是n型存储锁存装置的增益的一半，有利于适当的SRAM操作

公开(公告)号：US20050272195A1

公开(公告)日：2005-12-08

申请号：US11186748

申请日：2005-07-21

申请人： Andres Bryant ,  William Clark ,  David Fried ,  Mark Jaffe ,  Edward Nowak ,  John Pekarik ,  Christopher Putnam

发明人： Andres Bryant ,  William Clark ,  David Fried ,  Mark Jaffe ,  Edward Nowak ,  John Pekarik ,  Christopher Putnam

IPC分类号： H01L21/308 ,  H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L21/8232

CPC分类号： H01L21/84 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/823821 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/785 ,  Y10S438/947

摘要： A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin, and a second-type of FinFET which includes a second fin running parallel to the first fin. The invention also has an insulator fin positioned between the source/drain regions of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin and the second fin, such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET. The differences between the first impurity doping region and the second impurity doping region provide the gate with different work functions related to differences between the first-type of FinFET and the second-type of FinFET. The first fin and the second fin have approximately the same width.

摘要翻译： 公开了利用互补翅片型场效应晶体管（FinFET）的集成电路结构的方法和结构。 本发明具有包括第一鳍片的第一类型的FinFET和包括与第一鳍片平行的第二鳍片的第二类型的FinFET。 本发明还具有位于第一第一类型FinFET的源极/漏极区域和第二类型FinFET之间的绝缘体鳍片。 绝缘体鳍片具有与第一鳍片和第二鳍片大致相同的宽度尺寸，使得第一类型的FinFET和第二类型的FinFET之间的间隔大致等于一个鳍片的宽度。 本发明还具有形成在第一类型FinFET和第二类型FinFET的沟道区上的公共栅极。 栅极包括与第一类型的FinFET相邻的第一杂质掺杂区域和与第二类型的FinFET相邻的第二杂质掺杂区域。 第一杂质掺杂区域和第二杂质掺杂区域之间的差异为栅极提供与第一类型FinFET和第二类型FinFET之间的差异有关的不同功函数。 第一鳍片和第二鳍片具有大致相同的宽度。

公开(公告)号：US20050221543A1

公开(公告)日：2005-10-06

申请号：US11125063

申请日：2005-05-09

申请人： Andres Bryant ,  Meikei Ieong ,  K. Muller ,  Edward Nowak ,  David Fried ,  Jed Rankin

发明人： Andres Bryant ,  Meikei Ieong ,  K. Muller ,  Edward Nowak ,  David Fried ,  Jed Rankin

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L21/00

CPC分类号： H01L29/4908 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/66795 ,  H01L29/785

摘要： Accordingly, the present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention uses provides a double gated transistor with asymmetric gate doping, where one of the double gates is doped degenerately n-type and the other degenerately p-type. By doping on of the gates n-type, and the other p-type, the threshold voltage of the resulting device is improved. In particular, by asymmetrically doping the two gates, the resulting transistor can, with adequate doping of the body, have a threshold voltage in a range that enables low-voltage CMOS operation. For example, a transistor can be created that has a threshold voltage between 0V and 0.5V for nFETs and between 0 and −0.5V for pFETs.

摘要翻译： 因此，本发明提供一种双门控晶体管及其形成方法，其导致改进的器件性能和密度。 本发明的优选实施例提供了具有不对称栅极掺杂的双门控晶体管，其中双栅极中的一个被简并掺杂为n型，另一个为简并p型。 通过掺杂栅极n型和另一种p型，所得器件的阈值电压得到改善。 特别地，通过不对称地掺杂两个栅极，所得到的晶体管可以通过适当掺杂的体，在允许低电压CMOS操作的范围内具有阈值电压。 例如，可以产生对于nFET具有在0V和0.5V之间的阈值电压并且对于pFET而言在0和-0.5V之间的晶体管。

公开(公告)号：US20050001273A1

公开(公告)日：2005-01-06

申请号：US10604206

申请日：2003-07-01

申请人： Andres Bryant ,  William Clark ,  David Fried ,  Mark Jaffe ,  Edward Nowak ,  John Pekarik ,  Christopher Putnam

发明人： Andres Bryant ,  William Clark ,  David Fried ,  Mark Jaffe ,  Edward Nowak ,  John Pekarik ,  Christopher Putnam

IPC分类号： H01L21/308 ,  H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L33/00

CPC分类号： H01L21/84 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/823821 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/785 ,  Y10S438/947

摘要： A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin, and a second-type of FinFET which includes a second fin running parallel to the first fin. The invention also has an insulator fin positioned between the source/drain regions of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin and the second fin, such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET. The differences between the first impurity doping region and the second impurity doping region provide the gate with different work functions related to differences between the first-type of FinFET and the second-type of FinFET. The first fin and the second fin have approximately the same width.

摘要翻译： 公开了利用互补翅片型场效应晶体管（FinFET）的集成电路结构的方法和结构。 本发明具有包括第一鳍片的第一类型的FinFET和包括与第一鳍片平行的第二鳍片的第二类型的FinFET。 本发明还具有位于第一第一类型FinFET的源极/漏极区域和第二类型FinFET之间的绝缘体鳍片。 绝缘体鳍片具有与第一鳍片和第二鳍片大致相同的宽度尺寸，使得第一类型的FinFET和第二类型的FinFET之间的间隔大致等于一个鳍片的宽度。 本发明还具有形成在第一类型FinFET和第二类型FinFET的沟道区上的公共栅极。 栅极包括与第一类型的FinFET相邻的第一杂质掺杂区域和与第二类型的FinFET相邻的第二杂质掺杂区域。 第一杂质掺杂区域和第二杂质掺杂区域之间的差异为栅极提供与第一类型FinFET和第二类型FinFET之间的差异有关的不同功函数。 第一鳍片和第二鳍片具有大致相同的宽度。

公开(公告)号：US20130109454A1

公开(公告)日：2013-05-02

申请号：US13662176

申请日：2012-10-26

申请人： Lamar Wilkinson ,  David Fried

发明人： Lamar Wilkinson ,  David Fried

IPC分类号： A63F9/24

CPC分类号： G07F17/3293 ,  G07F17/3225 ,  G07F17/3237 ,  G07F17/3272

摘要： A method, computer system, and computer program product to implement an automatic fold-out command in an online card game. The system can automatically assign the player-entry of the player to a new table.

摘要翻译： 一种在在线纸牌游戏中实现自动折叠命令的方法，计算机系统和计算机程序产品。 系统可以自动将播放器的播放器条目分配给新的表。

公开(公告)号：US09779587B2

公开(公告)日：2017-10-03

申请号：US15431511

申请日：2017-02-13

申请人： Lamar Wilkinson ,  David Fried

发明人： Lamar Wilkinson ,  David Fried

IPC分类号： G07F17/32

CPC分类号： G07F17/3293 ,  G07F17/3225 ,  G07F17/3237 ,  G07F17/3272

摘要： A method, computer system, and computer program product to award one or more benchmark prizes in an online card game or hand. In certain embodiments, a controller automatically triggers awarding a first benchmark prize to at least one of one or more players or one or more game observers, based at least in part on an occurrence of a first benchmark event. The awarding occurs without any physical based-dealer taking time to payout the first benchmark prize, and thus, without slowing down the online game or hand that is being played.