公开(公告)号：US20100264489A1

公开(公告)日：2010-10-21

申请号：US12719475

申请日：2010-03-08

申请人： Hiroshi OHTA ,  Wataru SAITO ,  Syotaro ONO ,  Munehisa YABUZAKI ,  Nana HATANO ,  Miho WATANABE

发明人： Hiroshi OHTA ,  Wataru SAITO ,  Syotaro ONO ,  Munehisa YABUZAKI ,  Nana HATANO ,  Miho WATANABE

IPC分类号： H01L27/06 ,  H01L29/78

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/7395 ,  H01L29/7813

摘要： A transistor contains a first semiconductor layer of a first conductivity type and a drift layer having a pillar structure in which a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type are alternately disposed in a direction parallel to a surface of the first semiconductor layer. The fourth semiconductor layer of the first conductivity type and the fifth semiconductor layer of the second conductivity type are alternately disposed and parallel to the drift layer. The fifth semiconductor layer has a larger amount of impurities than the fourth semiconductor layer. The sixth semiconductor layer of the first conductivity type and the seventh semiconductor layer of the second conductivity type are alternately disposed and parallel to the fourth and the fifth semiconductor layers. The seventh semiconductor layer has a smaller amount of impurities than the sixth semiconductor layer.

摘要翻译： 晶体管包含第一导电类型的第一半导体层和具有柱结构的漂移层，其中第一导电类型的第二半导体层和第二导电类型的第三半导体层在平行于 第一半导体层的表面。 第一导电类型的第四半导体层和第二导电类型的第五半导体层交替地设置并平行于漂移层。 第五半导体层的杂质量比第四半导体层大。 第一导电类型的第六半导体层和第二导电类型的第七半导体层交替地设置并平行于第四和第五半导体层。 第七半导体层的杂质量比第六半导体层少。

公开(公告)号：US20100038712A1

公开(公告)日：2010-02-18

申请号：US12540192

申请日：2009-08-12

申请人： Miho WATANABE ,  Masaru IZUMISAWA ,  Yasuto SUMI ,  Hiroshi OHTA ,  Wataru SEKINE ,  Wataru SAITO ,  Syotaro ONO ,  Nana HATANO

发明人： Miho WATANABE ,  Masaru IZUMISAWA ,  Yasuto SUMI ,  Hiroshi OHTA ,  Wataru SEKINE ,  Wataru SAITO ,  Syotaro ONO ,  Nana HATANO

IPC分类号： H01L29/78

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/7802

摘要： A semiconductor device according to an embodiment of the present invention includes a device part and a terminal part. The device includes a first semiconductor layer, and second and third semiconductor layers formed on the first semiconductor layer, and alternately arranged along a direction parallel to a surface of the first semiconductor layer, wherein the device part is provided with a first region and a second region, each of which includes at least one of the second semiconductor layers and at least one of the third semiconductor layers, and with regard to a difference value ΔN (=NA−NB) obtained by subtracting an impurity amount NB per unit length of each of the third semiconductor layers from an impurity amount NA per unit length of each of the second semiconductor layers, a difference value ΔNC1 which is the difference value ΔN in the first region of the device part, a difference value ΔNC2 which is the difference value ΔN in the second region of the device part, and a difference value ΔNT which is the difference value ΔN in the terminal part satisfy a relationship of ΔNC1>ΔNT>ΔNC2.

摘要翻译： 根据本发明实施例的半导体器件包括器件部分和端子部分。 该器件包括第一半导体层，以及形成在第一半导体层上的第二和第三半导体层，并且沿着与第一半导体层的表面平行的方向交替布置，其中器件部分设置有第一区域和第二半导体层 区域，其中每一个包括第二半导体层和至少一个第三半导体层中的至少一个，并且关于通过从每单位长度减去杂质量NB获得的差值Dgr; N（= NA-NB） 从每个第二半导体层的每单位长度的杂质量NA中的每个第三半导体层的差分值＆Dgr; NC1，其是器件部分的第一区域中的差值＆Dgr; N，差值＆Dgr ;作为装置部分的第二区域中的差值Dgr; N的NC2，作为终端部分中的差值Dgr; N的差值＆Dgr; NT满足关系 的＆Dgr; NC1>＆Dgr; NT>＆Dgr; NC2。

公开(公告)号：US20090273031A1

公开(公告)日：2009-11-05

申请号：US12408415

申请日：2009-03-20

申请人： Wataru SAITO ,  Syotaro ONO ,  Nana HATANO ,  Masakatsu TAKASHITA ,  Hiroshi OHTA ,  Miho WATANABE

发明人： Wataru SAITO ,  Syotaro ONO ,  Nana HATANO ,  Masakatsu TAKASHITA ,  Hiroshi OHTA ,  Miho WATANABE

IPC分类号： H01L29/78

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095

摘要： A semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type provided on a major surface of the first semiconductor layer; a third semiconductor layer of a second conductivity type provided on the major surface of the first semiconductor layer, the third semiconductor layer forming a structure of periodical arrangement with the second semiconductor layer; a fourth semiconductor layer of the second conductivity type provided above the third semiconductor layer; a fifth semiconductor layer of the first conductivity type selectively provided on a surface of the fourth semiconductor layer; a first main electrode electrically connected to the first semiconductor layer; a second main electrode provided to contact a surface of the fifth semiconductor layer and a surface of the fourth semiconductor layer; and a control electrode provided above the fifth semiconductor layer, the fourth semiconductor layer, and the second semiconductor layer via an insulative film. A portion is provided locally in the third semiconductor layer, the portion depleting at a voltage not more than one third of a voltage at which the second semiconductor layer and the third semiconductor layer completely deplete.

摘要翻译： 半导体器件包括：第一导电类型的第一半导体层; 设置在第一半导体层的主表面上的第一导电类型的第二半导体层; 设置在所述第一半导体层的主表面上的第二导电类型的第三半导体层，所述第三半导体层形成与所述第二半导体层的周期性布置的结构; 设置在第三半导体层上方的第二导电类型的第四半导体层; 选择性地设置在第四半导体层的表面上的第一导电类型的第五半导体层; 电连接到第一半导体层的第一主电极; 设置成与所述第五半导体层的表面和所述第四半导体层的表面接触的第二主电极; 以及通过绝缘膜设置在第五半导体层，第四半导体层和第二半导体层上方的控制电极。 局部地设置在第三半导体层中的部分，其耗尽不超过第二半导体层和第三半导体层完全耗尽的电压的三分之一的电压。

公开(公告)号：US20100230745A1

公开(公告)日：2010-09-16

申请号：US12714002

申请日：2010-02-26

申请人： Wataru SAITO ,  Syotaro ONO ,  Hiroshi OHTA ,  Munehisa YABUZAKI ,  Nana HATANO ,  Miho WATANABE

发明人： Wataru SAITO ,  Syotaro ONO ,  Hiroshi OHTA ,  Munehisa YABUZAKI ,  Nana HATANO ,  Miho WATANABE

IPC分类号： H01L29/78 ,  H01L29/06

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/7395 ,  H01L29/861 ,  H01L29/8611

摘要： A power semiconductor device according to an embodiment of the present invention includes a first semiconductor layer of a first or second conductivity type, a second semiconductor layer of the first conductivity type formed on the first semiconductor layer, a third semiconductor layer of the second conductivity type selectively formed on a surface of the second semiconductor layer, at least one trench formed in a periphery of the third semiconductor layer on the surface of the second semiconductor layer, a depth of a bottom surface of the at least one trench being deeper than a bottom surface of the third semiconductor layer, and shallower than a top surface of the first semiconductor layer, and some or all of the at least one trench being in contact with a side surface of the third semiconductor layer, at least one insulator buried in the at least one trench, a first main electrode electrically connected to the first semiconductor layer, and a second main electrode electrically connected to the third semiconductor layer.

摘要翻译： 根据本发明实施例的功率半导体器件包括第一或第二导电类型的第一半导体层，形成在第一半导体层上的第一导电类型的第二半导体层，第二导电类型的第三半导体层 选择性地形成在第二半导体层的表面上，形成在第二半导体层的表面上的第三半导体层的周边中的至少一个沟槽，至少一个沟槽的底表面的深度比底部 表面，并且比第一半导体层的顶表面浅，并且至少一个沟槽的一些或全部与第三半导体层的侧表面接触，至少一个绝缘体埋在第三半导体层 至少一个沟槽，与第一半导体层电连接的第一主电极和电连接的第二主电极 引导到第三半导体层。

公开(公告)号：US20100102381A1

公开(公告)日：2010-04-29

申请号：US12553592

申请日：2009-09-03

申请人： Wataru SAITO ,  Syotaro ONO ,  Hiroshi OHTA ,  Munehisa YABUZAKI ,  Nana HATANO ,  Miho WATANABE

发明人： Wataru SAITO ,  Syotaro ONO ,  Hiroshi OHTA ,  Munehisa YABUZAKI ,  Nana HATANO ,  Miho WATANABE

IPC分类号： H01L29/78

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/7813

摘要： A power semiconductor device according to an embodiment of the present invention includes a first semiconductor layer of a first conductivity type, second semiconductor layers of the first conductivity type and third semiconductor layers of a second conductivity type, which are formed on the first semiconductor layer, have stripe shapes extending in a first horizontal direction, and are alternately arranged along a second horizontal direction orthogonal to the first horizontal direction, a fourth semiconductor layer of the second conductivity type, selectively formed on a surface of one of the third semiconductor layers, a fifth semiconductor layer of the first conductivity type, selectively formed on a surface of the fourth semiconductor layer, and formed into a stripe shape extending in the first horizontal direction without being formed into a stripe shape extending in the second horizontal direction, and a control electrode formed on the second, third, fourth, and fifth semiconductor layers via an insulating layer, and having a plane pattern periodical in the first horizontal direction and the second horizontal direction.

摘要翻译： 根据本发明实施例的功率半导体器件包括形成在第一半导体层上的第一导电类型的第一半导体层，第一导电类型的第二半导体层和第二导电类型的第三半导体层， 具有沿第一水平方向延伸的条纹形状，并且沿着与第一水平方向正交的第二水平方向交替排列，第二导电类型的第四半导体层选择性地形成在第三半导体层之一的表面上， 第一导电类型的第五半导体层，选择性地形成在第四半导体层的表面上，并且形成为在第一水平方向上延伸的条形，而不形成在第二水平方向上延伸的条形，以及控制电极 形成在第二，第三，第四和第五半导电体上 或层，并且具有在第一水平方向和第二水平方向上周期性的平面图案。

公开(公告)号：US20110018055A1

公开(公告)日：2011-01-27

申请号：US12840201

申请日：2010-07-20

申请人： Hiroshi OHTA ,  Yasuto SUMI ,  Kiyoshi KIMURA ,  Wataru SEKINE ,  Wataru SAITO ,  Syotaro ONO ,  Munehisa YABUZAKI ,  Nana HATANO ,  Miho WATANABE

发明人： Hiroshi OHTA ,  Yasuto SUMI ,  Kiyoshi KIMURA ,  Wataru SEKINE ,  Wataru SAITO ,  Syotaro ONO ,  Munehisa YABUZAKI ,  Nana HATANO ,  Miho WATANABE

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66712 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/7811

摘要： According to one embodiment, a power semiconductor device includes a first semiconductor layer, and first, second and third semiconductor regions. The first semiconductor layer has a first conductivity type. The first semiconductor regions have a second conductivity type, and are formed with periodicity in a lateral direction in a second semiconductor layer of the first conductivity type. The second semiconductor layer is provided on a major surface of the first semiconductor layer in a device portion with a main current path formed in a vertical direction generally perpendicular to the major surface and in a terminal portion provided around the device portion. The second semiconductor region has the first conductivity type and is a portion of the second semiconductor layer sandwiched between adjacent ones of the first semiconductor regions. The third semiconductor regions have the second conductivity type and are provided below the first semiconductor regions in the terminal portion.

摘要翻译： 根据一个实施例，功率半导体器件包括第一半导体层以及第一，第二和第三半导体区域。 第一半导体层具有第一导电类型。 第一半导体区域具有第二导电类型，并且在第一导电类型的第二半导体层中在横向方向上形成周期性。 第二半导体层设置在器件部分的第一半导体层的主表面上，其主电流通道形成在大体上垂直于主表面的垂直方向上，以及设置在器件部分周围的端子部分中。 第二半导体区域具有第一导电类型，并且是夹在相邻的第一半导体区域中的第二半导体层的一部分。 第三半导体区域具有第二导电类型并且设置在端子部分中的第一半导体区域的下方。

公开(公告)号：US20100096692A1

公开(公告)日：2010-04-22

申请号：US12537219

申请日：2009-08-06

申请人： Wataru SAITO ,  Syotaro ONO ,  Nana HATANO ,  Hiroshi OHTA ,  Miho WATANABE

发明人： Wataru SAITO ,  Syotaro ONO ,  Nana HATANO ,  Hiroshi OHTA ,  Miho WATANABE

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/7806

摘要： A semiconductor device of the invention includes: a super junction structure of an n-type pillar layer and a p-type pillar layer; a base layer provided on the p-type pillar layer; a source layer selectively provided on a surface of the base layer; a gate insulating film provided on a portion being in contact with the base layer, a portion being in contact with the source layer and a portion being in contact with the n-type pillar layer on a portion of a junction between the n-type pillar layer and the p-type pillar layer; a control electrode provided opposed to the base layer, the source layer and the n-type pillar layer through the gate insulating film; and a source electrode electrically connected to the base layer, the source layer and the n-type layer. The source electrode is contact with the surface of the n-type pillar layer located between the control electrodes to form a Schottky junction.

摘要翻译： 本发明的半导体器件包括：n型柱层和p型柱层的超结结构; 设置在p型支柱层上的基底层; 源层选择性地设置在基层的表面上; 设置在与所述基底层接触的部分上的栅极绝缘膜，与所述源极层接触的部分和在所述n型支柱的接合部的一部分上与所述n型支柱层接触的部分 层和p型支柱层; 控制电极，其通过所述栅极绝缘膜与所述基极层，所述源极层和所述n型支柱层相对设置; 以及与基极层，源极层和n型层电连接的源电极。 源电极与位于控制电极之间的n型支柱层的表面接触以形成肖特基结。

公开(公告)号：US20090236697A1

公开(公告)日：2009-09-24

申请号：US12403881

申请日：2009-03-13

申请人： Syotaro ONO ,  Wataru SAITO ,  Nana HATANO ,  Masaru IZUMISAWA ,  Yasuto SUMI ,  Hiroshi OHTA ,  Wataru SEKINE ,  Miho WATANABE

发明人： Syotaro ONO ,  Wataru SAITO ,  Nana HATANO ,  Masaru IZUMISAWA ,  Yasuto SUMI ,  Hiroshi OHTA ,  Wataru SEKINE ,  Miho WATANABE

IPC分类号： H01L29/06 ,  H01L21/20

CPC分类号： H01L29/66712 ,  H01L21/266 ,  H01L29/0615 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/7395 ,  H01L29/7811

摘要： A semiconductor device includes a super junction region that has a first-conductivity-type first semiconductor pillar region and a second-conductivity-type second semiconductor pillar region alternately provided on the semiconductor substrate. The first semiconductor pillar region and the second semiconductor pillar region in a termination region have a lamination form resulting from alternate lamination of the first semiconductor pillar region and the second semiconductor pillar region on the top surface of the semiconductor substrate. The first semiconductor pillar region and/or the second semiconductor pillar region at a corner part of the termination region exhibit an impurity concentration distribution such that a plurality of impurity concentration peaks appear periodically. The first semiconductor pillar region and/or the second semiconductor pillar region at a corner part of the termination region have an impurity amount such that it becomes smaller as being closer to the circumference of the corner part.

摘要翻译： 半导体器件包括具有交替设置在半导体衬底上的第一导电型第一半导体柱区域和第二导电型第二半导体柱区域的超结区域。 终端区域中的第一半导体柱区域和第二半导体柱区域具有由半导体衬底的顶表面上的第一半导体柱区域和第二半导体柱区域的交替层叠形成的叠层形式。 终端区域的角部处的第一半导体柱区域和/或第二半导体柱区域显示杂质浓度分布，使得多个杂质浓度峰值周期性出现。 终端区域的角部处的第一半导体柱区域和/或第二半导体柱区域具有使得随着角部更靠近圆周而变小的杂质量。

公开(公告)号：US20100308399A1

公开(公告)日：2010-12-09

申请号：US12728823

申请日：2010-03-22

申请人： Wataru SAITO ,  Syotaro ONO ,  Munehisa YABUZAKI ,  Nana HATANO ,  Miho WATANABE

发明人： Wataru SAITO ,  Syotaro ONO ,  Munehisa YABUZAKI ,  Nana HATANO ,  Miho WATANABE

IPC分类号： H01L29/78

CPC分类号： H01L29/7802 ,  H01L29/0619 ,  H01L29/0626 ,  H01L29/0634 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7828

摘要： A power semiconductor device includes: a first semiconductor layer of the first conduction type; second semiconductor layers of the first conduction type and third semiconductor layers of the second conduction type alternately provided transversely on the first semiconductor layer; fourth semiconductor layers of the second conduction type provided on the surfaces of the third semiconductor layers; fifth semiconductor layers of the first conduction type provided selectively on the surfaces of the fourth semiconductor layer; sixth semiconductor layers of the second conduction type and seventh semiconductor layers of the first conduction type alternately provided transversely on the second and the third semiconductor layers; a first main electrode electrically connected to the first semiconductor layer; an insulation film provided on the fourth semiconductor layers, the sixth semiconductor layers and the seventh semiconductor layers; a control electrode provided on the fourth semiconductor layers, the sixth semiconductor layers and the seventh semiconductor layers via the insulation film; and a second main electrode joined to the surfaces of the fourth semiconductor layers and the fifth semiconductor layers, the sixth semiconductor layers being connected to the fourth semiconductor layers and to at least one of the third semiconductor layers, which is provided between two of the fourth semiconductor layers, and an impurity concentration of the third semiconductor layers provided below the sixth semiconductor layers being higher than an impurity concentration of the third semiconductor layers provided under the fourth semiconductor layers.

摘要翻译： 功率半导体器件包括：第一导电类型的第一半导体层; 第一导电类型的第二半导体层和第二导电类型的第三半导体层交替地设置在第一半导体层上; 设置在第三半导体层的表面上的第二导电类型的第四半导体层; 选择性地在第四半导体层的表面上提供第一导电类型的第五半导体层; 第二导电类型的第六半导体层和第一导电类型的第七半导体层交替地设置在第二和第三半导体层上; 电连接到第一半导体层的第一主电极; 设置在第四半导体层，第六半导体层和第七半导体层上的绝缘膜; 设置在第四半导体层上的控制电极，第六半导体层和第七半导体层经由绝缘膜; 以及与所述第四半导体层和所述第五半导体层的表面接合的第二主电极，所述第六半导体层与所述第四半导体层连接，并且至少一个所述第三半导体层设置在所述第四半导体层 并且设置在第六半导体层下方的第三半导体层的杂质浓度高于设置在第四半导体层下方的第三半导体层的杂质浓度。

公开(公告)号：US20110049615A1

公开(公告)日：2011-03-03

申请号：US12862490

申请日：2010-08-24

申请人： Wataru SAITO ,  Syotaro ONO ,  Munehisa YABUZAKI ,  Nana HATANO ,  Miho WATANABE

发明人： Wataru SAITO ,  Syotaro ONO ,  Munehisa YABUZAKI ,  Nana HATANO ,  Miho WATANABE

IPC分类号： H01L29/78

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/7843

摘要： According to one embodiment, a power semiconductor device includes a second semiconductor layer of a first conductivity type and a third semiconductor layer of a second conductivity type periodically disposed repeatedly along a surface of the first semiconductor layer on a first semiconductor layer of the first conductivity type. A first main electrode is provided to electrically connect to the first semiconductor layer. A fourth semiconductor layer of the second conductivity type is provided to connect to the third semiconductor layer. Fifth semiconductor layers of the first conductivity type are selectively provided in the fourth semiconductor layer surface. A second main electrode is provided on a surface of the fourth and fifth semiconductor layers. A control electrode is provided on a surface of the fourth, fifth, and second semiconductor layers via a gate insulating film. First insulating films are provided by filling a trench made in the second semiconductor layer.

摘要翻译： 根据一个实施例，功率半导体器件包括第一导电类型的第二半导体层和在第一导电类型的第一半导体层上沿着第一半导体层的表面周期性地重复设置的第二导电类型的第三半导体层 。 提供第一主电极以电连接到第一半导体层。 提供第二导电类型的第四半导体层以连接到第三半导体层。 在第四半导体层表面中选择性地设置第一导电类型的第五半导体层。 第二主电极设置在第四和第五半导体层的表面上。 控制电极经由栅极绝缘膜设置在第四，第五和第二半导体层的表面上。 通过填充在第二半导体层中制成的沟槽来提供第一绝缘膜。