公开(公告)号：US5364817A

公开(公告)日：1994-11-15

申请号：US238664

申请日：1994-05-05

申请人： Water Lur ,  Cheng-Han Huang ,  Shih-Chanh Chang ,  Liang-Chih Lin

发明人： Water Lur ,  Cheng-Han Huang ,  Shih-Chanh Chang ,  Liang-Chih Lin

IPC分类号： H01L21/285 ,  H01L21/283

CPC分类号： H01L21/28512

摘要： A method of metallization using a tungsten plug is described. A contact hole is opened to the semiconductor substrate through an insulating layer covering semiconductor structures in and on the semiconductor substrate. A glue layer is deposited conformally over the surface of the insulating layer and within the contact opening. A tungsten plug is formed within the contact opening. The glue layer is removed except for portions of the glue layer underneath the tungsten plug and on the lower sides of the tungsten plug. Ditches are left on the upper sides of the tungsten plug where the glue layer has been removed. The ditches around the tungsten plug are filled with a dielectric material. A second metallization is deposited and patterned. The patterned second metallization does not extend over one side portion of the tungsten plug; that is, there is no dog-bone formation. There is no junction damage through the side portion of the tungsten plug not covered by the second metallization because the dielectric material filling the ditches protects the glue layer from being etched away. In a second embodiment of the invention, after the contact hole is opened, the insulating layer is reflowed forming an overhang around the contact hole. A glue layer is deposited conformally over the surface of the insulating layer and within the contact opening. A tungsten plug is formed within the contact opening.

摘要翻译： 描述了使用钨丝塞的金属化方法。 通过覆盖半导体衬底中半导体结构的绝缘层向半导体衬底开口接触孔。 粘合剂层保形地沉积在绝缘层的表面上并且在接触开口内。 在接触开口内形成钨塞。 除了钨丝塞下方的胶水层的部分和钨丝塞的下侧外，胶层除去。 沟槽留在已经去除胶层的钨插头的上侧。 钨插塞周围的沟槽填充有电介质材料。 沉积和图案化第二金属化。 图案化的第二金属化不在钨塞的一个侧面上延伸; 也就是说，没有狗骨形成。 由于填充沟槽的电介质材料保护胶层不会被蚀刻掉，所以没有被第二金属化覆盖的钨塞的侧部没有结损坏。 在本发明的第二实施例中，在接触孔打开之后，绝缘层被回流，在接触孔周围形成伸出。 粘合剂层保形地沉积在绝缘层的表面上并且在接触开口内。 在接触开口内形成钨塞。

公开(公告)号：US5739046A

公开(公告)日：1998-04-14

申请号：US657058

申请日：1996-05-28

申请人： Water Lur ,  Shih-Chanh Chang ,  Jiun Yuan Wu ,  Der Yuan Wu

发明人： Water Lur ,  Shih-Chanh Chang ,  Jiun Yuan Wu ,  Der Yuan Wu

IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76864 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76856

摘要： A new method of forming a metal diffusion barrier layer is described. Semiconductor device structures are formed in and on a semiconductor substrate. At least one dielectric layer covers the semiconductor structures and at least one contact hole has been opened through the dielectric layer(s) to the semiconductor substrate. A metal diffusion barrier layer is now formed using the following steps: In the first step, a thin layer of titanium is deposited conformally over the surface of the dielectric layer(s) and within the contact opening(s) and annealed in a nitrogen atmosphere at a temperature of between about 580.degree. to 630.degree. C. for between about 20 to 120 seconds. The second step is to form stable and adhesive titanium compounds on the pre-metal dielectric layer as well as to form a low resistance silicide on the contact silicon by annealing at between about 800.degree. to 900.degree. C. for between about 5 to 60 seconds. The final step is to release the system stress by tempering the layer at a temperature of between about 600.degree. to 750.degree. C. This completes the barrier layer which has good adhesion to the dielectric layer(s) and, therefore, promotes improved pad bonding yield.

摘要翻译： 描述形成金属扩散阻挡层的新方法。 在半导体衬底中形成半导体器件结构。 至少一个电介质层覆盖半导体结构，并且至少一个接触孔已经通过介电层被打开到半导体衬底。 现在通过以下步骤形成金属扩散阻挡层：在第一步骤中，将薄的钛层保形地沉积在电介质层的表面和接触开口内，并在氮气气氛中退火 在约580℃至630℃之间的温度下进行约20至120秒。 第二步是在金属前介电层上形成稳定且粘合的钛化合物，并在接触硅上形成低电阻硅化物，在约800-900℃之间退火约5至60秒 。 最后一步是通过在约600至750℃的温度下回火层来释放系统应力。这完成了与电介质层具有良好粘附性的阻挡层，因此促进改进的焊盘接合 产量。

公开(公告)号：US5895252A

公开(公告)日：1999-04-20

申请号：US552209

申请日：1995-11-02

申请人： Water Lur ,  Cheng Han Huang

发明人： Water Lur ,  Cheng Han Huang

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76213 ,  Y10S438/966

摘要： A method of forming a field oxide isolation region is described, in which a masking layer is formed over a silicon substrate. The masking layer is patterned to form an opening for the field oxide isolation region, whereby the remainder of the masking layer forms an implant mask. A conductivity-imparting dopant is implanted through the opening into the silicon substrate. Oxygen is implanted through the opening into the silicon substrate in multiple implantation steps. The implant mask is removed. The field oxide isolation region is formed in and on the silicon substrate, by annealing in a non-oxygen ambient. Alternately, the field oxide isolation region is formed by annealing in oxygen, simultaneously forming a gate oxide in the region between the field oxide isolation regions.

摘要翻译： 描述了形成场氧化物隔离区域的方法，其中在硅衬底上形成掩模层。 图案化掩模层以形成用于场氧化物隔离区的开口，由此掩模层的其余部分形成植入掩模。 通过开口将导电性赋予掺杂剂注入到硅衬底中。 在多个注入步骤中，氧气通过开口注入硅衬底。 移除植入物掩模。 通过在非氧环境中退火，在硅衬底中和硅衬底上形成场氧化物隔离区。 或者，通过在氧中退火而形成场氧化物隔离区，同时在场氧化物隔离区之间的区域中形成栅极氧化物。

公开(公告)号：US5472903A

公开(公告)日：1995-12-05

申请号：US247989

申请日：1994-05-24

申请人： Water Lur ,  Cheng-Han Huang

发明人： Water Lur ,  Cheng-Han Huang

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76208

摘要： A new isolation technology fabrication process is provided including the step of forming a trench in a semiconductor material. Then, several poly walls are formed in the trench. The poly walls are oxidized to form a single oxide isolation region filling the trench.

摘要翻译： 提供了一种新的隔离技术制造方法，包括在半导体材料中形成沟槽的步骤。 然后，在沟槽中形成几个多壁。 多壁氧化形成填充沟槽的单一氧化物隔离区。

公开(公告)号：US5449630A

公开(公告)日：1995-09-12

申请号：US275432

申请日：1994-07-15

申请人： Water Lur ,  Cheng-Han Huang

发明人： Water Lur ,  Cheng-Han Huang

IPC分类号： H01L21/334 ,  H01L27/108 ,  H01L21/8242

CPC分类号： H01L29/66181 ,  H01L27/10829

摘要： A capacitor structure suitable for use in Dynamic Random Access Memory (DRAM) Integrated Circuit (IC) devices and its method of fabrication is disclosed. The capacitor includes a main or root trench extending vertically into the silicon substrate and at least one buried trench extending horizontally into the side wall of the main trench. The enlarged trench sidewall surface area as a result of the added buried trenches increases the total capacitance of the capacitor and it suitable for use with high density, high data volume memory devices. The buried trenches are formed by implanting oxygen or nitrogen ions into the designated depths of the silicon substrate, subsequently annealing the entire substrate at the absence of gaseous oxygen, and etching away the converted silicon dioxide or silicon nitride. The formed trench system can reduce the accumulation of the structural stress to avoid the formation of crystalline defects and obtain the resulting device with better quality.

摘要翻译： 公开了一种适用于动态随机存取存储器（DRAM）集成电路（IC）器件及其制造方法的电容器结构。 电容器包括垂直延伸到硅衬底中的主沟槽或根沟槽以及水平地延伸到主沟槽的侧壁中的至少一个埋入沟槽。 作为添加的掩埋沟槽的结果，扩大的沟槽侧壁表面积增加了电容器的总电容，并且它适合于与高密度，高数据量的存储器件一起使用。 通过将氧或氮离子注入到硅衬底的指定深度中，随后在不存在氧气的情况下对整个衬底进行退火并蚀刻掉转换的二氧化硅或氮化硅来形成掩埋沟槽。 形成的沟槽系统可以减少结构应力的积累，避免晶体缺陷的形成，从而获得更好质量的结果。

公开(公告)号：US5668394A

公开(公告)日：1997-09-16

申请号：US582599

申请日：1996-01-03

申请人： Water Lur ,  Cheng-Han Huang

发明人： Water Lur ,  Cheng-Han Huang

IPC分类号： H01L21/28 ,  H01L29/49 ,  H01L29/76

CPC分类号： H01L29/4941 ,  H01L21/28061 ,  Y10S257/915

摘要： A new method of fabricating a polycide gate is described. A gate polysilicon layer is provided a gate oxide layer on the surface of a substrate. A thin conducting diffusion barrier is deposited overlying the gate polysilicon layer. A of tungsten silicide is deposited overlying the thin diffusion barrier layer wherein a reaction gas in the deposition contains fluorine atoms and wherein fluorine atoms are incorporated into the tungsten layer. The gate polysilicon, thin conducting barrier, and tungsten silicide layers are patterned form the polycide gate structures. The wafer is annealed complete formation of the polycide gate structures wherein number of fluorine atoms from the tungsten silicide layer into the gate polysilicon layer are minimized by presence of the thin conducting diffusion barrier layer wherein because the diffusion of the fluorine atoms is the thickness of the gate oxide layer does not This prevents the device from degradation such as voltage shift and saturation current descrease.

摘要翻译： 描述了一种制造多晶硅栅极的新方法。 栅极多晶硅层在衬底的表面上提供栅极氧化物层。 沉积在栅极多晶硅层上的薄导电扩散势垒。 沉积硅化硅的A，覆盖薄扩散阻挡层，其中沉积中的反应气体含有氟原子，并且其中氟原子被结合到钨层中。 门多晶硅，薄导电屏障和硅化钨层由多晶硅栅极结构构图。 晶片经过退火完成形成多晶硅栅极结构，其中从硅化钨层到栅极多晶硅层的氟原子数量通过存在薄导电扩散阻挡层而最小化，其中由于氟原子的扩散是 栅极氧化层不会阻止器件劣化，如电压偏移和饱和电流下降。

公开(公告)号：US5364803A

公开(公告)日：1994-11-15

申请号：US80304

申请日：1993-06-24

申请人： Water Lur ,  Cheng-Han Huang

发明人： Water Lur ,  Cheng-Han Huang

IPC分类号： H01L21/28 ,  H01L29/49 ,  H01L21/265

CPC分类号： H01L29/4941 ,  H01L21/28061 ,  Y10S257/915

摘要： A new method of fabricating a polycide gate structure is described. A gate polysilicon layer is provided overlying a gate oxide layer on the surface of a semiconductor substrate. A thin conducting diffusion barrier layer is deposited overlying the gate polysilicon layer. A layer of tungsten silicide is deposited overlying the thin conducting diffusion barrier layer wherein a reaction gas used in the deposition contains fluorine atoms and wherein the fluorine atoms are incorporated into the tungsten silicide layer. The gate polysilicon, thin conducting diffusion barrier, and tungsten silicide layers are patterned to form the polycide gate structures. The wafer is annealed to complete formation of the polycide gate structures wherein the number of fluorine atoms from the tungsten silicide layer diffusing into the gate polysilicon layer are minimized by the presence of the thin conducting diffusion barrier layer and wherein because the diffusion of the fluorine atoms is minimized, the thickness of the gate oxide layer does not increase. This prevents the device from degradation such as threshold voltage shift and saturation current decrease.

摘要翻译： 描述了一种制造多晶硅栅极结构的新方法。 栅极多晶硅层设置在半导体衬底的表面上覆盖栅极氧化物层。 沉积在栅极多晶硅层上的薄导电扩散阻挡层。 一层硅化钨沉积在薄导电扩散阻挡层上，其中沉积中使用的反应气体含有氟原子，并且其中氟原子被结合到硅化钨层中。 栅极多晶硅，薄导电扩散阻挡层和硅化钨层被图案化以形成多晶硅栅极结构。 将晶片退火以完成多晶硅栅极结构的形成，其中通过薄导电扩散阻挡层的存在使扩散到栅极多晶硅层中的硅化钨层的氟原子的数量最小化，并且其中由于氟原子的扩散 栅极氧化物层的厚度不会增加。 这防止器件劣化，例如阈值电压偏移和饱和电流降低。

公开(公告)号：US5459095A

公开(公告)日：1995-10-17

申请号：US233646

申请日：1994-04-26

申请人： Cheng-Han Huang ,  Water Lur

发明人： Cheng-Han Huang ,  Water Lur

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  Y10S438/947

摘要： A MOS capacitor structure in accordance with the invention is formed by depositing a polysilicon electrode layer on the substrate. Oxide regions are then formed on the polysilicon layer. Using the oxide regions as a mask, pillars are etched in the polysilicon electrode layer.

摘要翻译： 根据本发明的MOS电容器结构通过在衬底上沉积多晶硅电极层而形成。 然后在多晶硅层上形成氧化物区域。 使用氧化物区域作为掩模，在多晶硅电极层中蚀刻柱。

公开(公告)号：US08062536B2

公开(公告)日：2011-11-22

申请号：US12729234

申请日：2010-03-22

申请人： Chih-Chien Liu ,  Ta-Shan Tseng ,  Wen-Bin Shieh ,  Juan-Yuan Wu ,  Water Lur ,  Shih-Wei Sun

发明人： Chih-Chien Liu ,  Ta-Shan Tseng ,  Wen-Bin Shieh ,  Juan-Yuan Wu ,  Water Lur ,  Shih-Wei Sun

IPC分类号： H01L21/467 ,  H01L21/32 ,  H01L21/308 ,  H01L21/762

CPC分类号： H01L21/02112 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/0276 ,  H01L21/31612 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76838

摘要： A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.

摘要翻译： 在形成半导体器件时，将介电材料沉积在布线之间的间隙中的方法包括形成盖层并形成间隙，沉积高密度等离子体化学气相沉积（HDPCVD）电介质材料。 第一和第二抗反射涂层可以形成在布线层上，第一和第二抗反射涂层由不同的材料制成。 防反射涂层和布线层都被蚀刻通过以形成由间隙分开的布线。 可以使用高密度等离子体化学气相沉积来填充布线之间的间隙。

公开(公告)号：US07378740B2

公开(公告)日：2008-05-27

申请号：US11196038

申请日：2005-08-02

申请人： Tri-Rung Yew ,  Yimin Huang ,  Water Lur ,  Shih-Wei Sun

发明人： Tri-Rung Yew ,  Yimin Huang ,  Water Lur ,  Shih-Wei Sun

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/7681 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An improved dual damascene structure is provided for use in the wiring-line structures of multi-level interconnects in integrated circuit. In this dual damascene structure, low-K (low dielectric constant) dielectric materials are used to form both the di-electric layers and the etch-stop layers between the metal interconnects in the IC device. With this feature, the dual damascene structure can prevent high parasite capacitance to occur therein that would otherwise cause large RC delay to the signals being transmitted through the metal interconnects and thus degrade the performance of the IC device. With the dual damascene structure, such parasite capacitance can be reduced, thus assuring the performance of the IC device.

摘要翻译： 提供了一种改进的双镶嵌结构，用于集成电路中多级互连的布线结构。 在这种双镶嵌结构中，使用低K（低介电常数）介电材料来形成IC器件中的金属互连之间的二电层和蚀刻停止层。 利用该特征，双镶嵌结构可以防止在其中发生高的寄生电容，否则会对通过金属互连传输的信号造成较大的RC延迟，从而降低IC器件的性能。 利用双镶嵌结构，可以减少这种寄生电容，从而确保IC器件的性能。