公开(公告)号：US5364817A

公开(公告)日：1994-11-15

申请号：US238664

申请日：1994-05-05

Applicant: Water Lur ,  Cheng-Han Huang ,  Shih-Chanh Chang ,  Liang-Chih Lin

Inventor： Water Lur ,  Cheng-Han Huang ,  Shih-Chanh Chang ,  Liang-Chih Lin

IPC: H01L21/285 ,  H01L21/283

CPC classification number: H01L21/28512

Abstract: A method of metallization using a tungsten plug is described. A contact hole is opened to the semiconductor substrate through an insulating layer covering semiconductor structures in and on the semiconductor substrate. A glue layer is deposited conformally over the surface of the insulating layer and within the contact opening. A tungsten plug is formed within the contact opening. The glue layer is removed except for portions of the glue layer underneath the tungsten plug and on the lower sides of the tungsten plug. Ditches are left on the upper sides of the tungsten plug where the glue layer has been removed. The ditches around the tungsten plug are filled with a dielectric material. A second metallization is deposited and patterned. The patterned second metallization does not extend over one side portion of the tungsten plug; that is, there is no dog-bone formation. There is no junction damage through the side portion of the tungsten plug not covered by the second metallization because the dielectric material filling the ditches protects the glue layer from being etched away. In a second embodiment of the invention, after the contact hole is opened, the insulating layer is reflowed forming an overhang around the contact hole. A glue layer is deposited conformally over the surface of the insulating layer and within the contact opening. A tungsten plug is formed within the contact opening.

Abstract translation: 描述了使用钨丝塞的金属化方法。 通过覆盖半导体衬底中半导体结构的绝缘层向半导体衬底开口接触孔。 粘合剂层保形地沉积在绝缘层的表面上并且在接触开口内。 在接触开口内形成钨塞。 除了钨丝塞下方的胶水层的部分和钨丝塞的下侧外，胶层除去。 沟槽留在已经去除胶层的钨插头的上侧。 钨插塞周围的沟槽填充有电介质材料。 沉积和图案化第二金属化。 图案化的第二金属化不在钨塞的一个侧面上延伸; 也就是说，没有狗骨形成。 由于填充沟槽的电介质材料保护胶层不会被蚀刻掉，所以没有被第二金属化覆盖的钨塞的侧部没有结损坏。 在本发明的第二实施例中，在接触孔打开之后，绝缘层被回流，在接触孔周围形成伸出。 粘合剂层保形地沉积在绝缘层的表面上并且在接触开口内。 在接触开口内形成钨塞。

公开(公告)号：US5668394A

公开(公告)日：1997-09-16

申请号：US582599

申请日：1996-01-03

Applicant: Water Lur ,  Cheng-Han Huang

Inventor： Water Lur ,  Cheng-Han Huang

IPC: H01L21/28 ,  H01L29/49 ,  H01L29/76

CPC classification number: H01L29/4941 ,  H01L21/28061 ,  Y10S257/915

Abstract: A new method of fabricating a polycide gate is described. A gate polysilicon layer is provided a gate oxide layer on the surface of a substrate. A thin conducting diffusion barrier is deposited overlying the gate polysilicon layer. A of tungsten silicide is deposited overlying the thin diffusion barrier layer wherein a reaction gas in the deposition contains fluorine atoms and wherein fluorine atoms are incorporated into the tungsten layer. The gate polysilicon, thin conducting barrier, and tungsten silicide layers are patterned form the polycide gate structures. The wafer is annealed complete formation of the polycide gate structures wherein number of fluorine atoms from the tungsten silicide layer into the gate polysilicon layer are minimized by presence of the thin conducting diffusion barrier layer wherein because the diffusion of the fluorine atoms is the thickness of the gate oxide layer does not This prevents the device from degradation such as voltage shift and saturation current descrease.

Abstract translation: 描述了一种制造多晶硅栅极的新方法。 栅极多晶硅层在衬底的表面上提供栅极氧化物层。 沉积在栅极多晶硅层上的薄导电扩散势垒。 沉积硅化硅的A，覆盖薄扩散阻挡层，其中沉积中的反应气体含有氟原子，并且其中氟原子被结合到钨层中。 门多晶硅，薄导电屏障和硅化钨层由多晶硅栅极结构构图。 晶片经过退火完成形成多晶硅栅极结构，其中从硅化钨层到栅极多晶硅层的氟原子数量通过存在薄导电扩散阻挡层而最小化，其中由于氟原子的扩散是 栅极氧化层不会阻止器件劣化，如电压偏移和饱和电流下降。

公开(公告)号：US5364803A

公开(公告)日：1994-11-15

申请号：US80304

申请日：1993-06-24

Applicant: Water Lur ,  Cheng-Han Huang

Inventor： Water Lur ,  Cheng-Han Huang

IPC: H01L21/28 ,  H01L29/49 ,  H01L21/265

CPC classification number: H01L29/4941 ,  H01L21/28061 ,  Y10S257/915

Abstract: A new method of fabricating a polycide gate structure is described. A gate polysilicon layer is provided overlying a gate oxide layer on the surface of a semiconductor substrate. A thin conducting diffusion barrier layer is deposited overlying the gate polysilicon layer. A layer of tungsten silicide is deposited overlying the thin conducting diffusion barrier layer wherein a reaction gas used in the deposition contains fluorine atoms and wherein the fluorine atoms are incorporated into the tungsten silicide layer. The gate polysilicon, thin conducting diffusion barrier, and tungsten silicide layers are patterned to form the polycide gate structures. The wafer is annealed to complete formation of the polycide gate structures wherein the number of fluorine atoms from the tungsten silicide layer diffusing into the gate polysilicon layer are minimized by the presence of the thin conducting diffusion barrier layer and wherein because the diffusion of the fluorine atoms is minimized, the thickness of the gate oxide layer does not increase. This prevents the device from degradation such as threshold voltage shift and saturation current decrease.

Abstract translation: 描述了一种制造多晶硅栅极结构的新方法。 栅极多晶硅层设置在半导体衬底的表面上覆盖栅极氧化物层。 沉积在栅极多晶硅层上的薄导电扩散阻挡层。 一层硅化钨沉积在薄导电扩散阻挡层上，其中沉积中使用的反应气体含有氟原子，并且其中氟原子被结合到硅化钨层中。 栅极多晶硅，薄导电扩散阻挡层和硅化钨层被图案化以形成多晶硅栅极结构。 将晶片退火以完成多晶硅栅极结构的形成，其中通过薄导电扩散阻挡层的存在使扩散到栅极多晶硅层中的硅化钨层的氟原子的数量最小化，并且其中由于氟原子的扩散 栅极氧化物层的厚度不会增加。 这防止器件劣化，例如阈值电压偏移和饱和电流降低。

公开(公告)号：US5472903A

公开(公告)日：1995-12-05

申请号：US247989

申请日：1994-05-24

Applicant: Water Lur ,  Cheng-Han Huang

Inventor： Water Lur ,  Cheng-Han Huang

IPC: H01L21/762 ,  H01L21/76

CPC classification number: H01L21/76208

Abstract: A new isolation technology fabrication process is provided including the step of forming a trench in a semiconductor material. Then, several poly walls are formed in the trench. The poly walls are oxidized to form a single oxide isolation region filling the trench.

Abstract translation: 提供了一种新的隔离技术制造方法，包括在半导体材料中形成沟槽的步骤。 然后，在沟槽中形成几个多壁。 多壁氧化形成填充沟槽的单一氧化物隔离区。

公开(公告)号：US5449630A

公开(公告)日：1995-09-12

申请号：US275432

申请日：1994-07-15

Applicant: Water Lur ,  Cheng-Han Huang

Inventor： Water Lur ,  Cheng-Han Huang

IPC: H01L21/334 ,  H01L27/108 ,  H01L21/8242

CPC classification number: H01L29/66181 ,  H01L27/10829

Abstract: A capacitor structure suitable for use in Dynamic Random Access Memory (DRAM) Integrated Circuit (IC) devices and its method of fabrication is disclosed. The capacitor includes a main or root trench extending vertically into the silicon substrate and at least one buried trench extending horizontally into the side wall of the main trench. The enlarged trench sidewall surface area as a result of the added buried trenches increases the total capacitance of the capacitor and it suitable for use with high density, high data volume memory devices. The buried trenches are formed by implanting oxygen or nitrogen ions into the designated depths of the silicon substrate, subsequently annealing the entire substrate at the absence of gaseous oxygen, and etching away the converted silicon dioxide or silicon nitride. The formed trench system can reduce the accumulation of the structural stress to avoid the formation of crystalline defects and obtain the resulting device with better quality.

Abstract translation: 公开了一种适用于动态随机存取存储器（DRAM）集成电路（IC）器件及其制造方法的电容器结构。 电容器包括垂直延伸到硅衬底中的主沟槽或根沟槽以及水平地延伸到主沟槽的侧壁中的至少一个埋入沟槽。 作为添加的掩埋沟槽的结果，扩大的沟槽侧壁表面积增加了电容器的总电容，并且它适合于与高密度，高数据量的存储器件一起使用。 通过将氧或氮离子注入到硅衬底的指定深度中，随后在不存在氧气的情况下对整个衬底进行退火并蚀刻掉转换的二氧化硅或氮化硅来形成掩埋沟槽。 形成的沟槽系统可以减少结构应力的积累，避免晶体缺陷的形成，从而获得更好质量的结果。

公开(公告)号：US5459095A

公开(公告)日：1995-10-17

申请号：US233646

申请日：1994-04-26

Applicant: Cheng-Han Huang ,  Water Lur

Inventor： Cheng-Han Huang ,  Water Lur

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10817 ,  Y10S438/947

Abstract: A MOS capacitor structure in accordance with the invention is formed by depositing a polysilicon electrode layer on the substrate. Oxide regions are then formed on the polysilicon layer. Using the oxide regions as a mask, pillars are etched in the polysilicon electrode layer.

Abstract translation: 根据本发明的MOS电容器结构通过在衬底上沉积多晶硅电极层而形成。 然后在多晶硅层上形成氧化物区域。 使用氧化物区域作为掩模，在多晶硅电极层中蚀刻柱。

公开(公告)号：US06403487B1

公开(公告)日：2002-06-11

申请号：US08991192

申请日：1997-12-16

Applicant: Cheng-Han Huang ,  Meng-Jin Tsai ,  Cheng-Jung Hsu ,  Po-Hung Chen

Inventor： Cheng-Han Huang ,  Meng-Jin Tsai ,  Cheng-Jung Hsu ,  Po-Hung Chen

IPC: H01L21302

CPC classification number: H01L21/823468 ,  H01L21/823456 ,  H01L27/105 ,  H01L29/6653

Abstract: A method is provided for forming separated spacer structures in a mixed-mode integrated circuit, which can be used to form spacer structures with different widths for the various kinds of devices in the mixed-mode integrated circuit. The method is for use on a semiconductor substrate which is formed with at least a first gate for a first kind of device of the mixed-mode integrated circuit and a second gate for a second kind of device of the integrated circuit, with the second gate being larger in width than the first gate such that the first gate is formed with a first spacer structure on the sidewalls thereof to a first desired width while the second gate is formed with a second spacer structure on the sidewalls thereof to a second desired width larger than the first desired width. The method features a two-step etching process in which the first etching process is performed to form one spacer structure to the first desired width, while the second etching process is performed to form the other spacer structure to the second desired width.

Abstract translation: 提供了一种用于在混合模式集成电路中形成分离的间隔结构的方法，其可用于形成用于混合模式集成电路中的各种装置的具有不同宽度的间隔结构。 该方法用于半导体衬底，该半导体衬底至少形成用于混合模式集成电路的第一种器件的第一栅极和集成电路的第二种器件的第二栅极，第二栅极 宽度大于第一栅极，使得第一栅极在其侧壁上形成具有第一间隔结构的第一期望宽度，而第二栅极在其侧壁上形成第二间隔结构，使其具有更大的第二期望宽度 比第一个期望的宽度。 该方法具有两步蚀刻工艺，其中执行第一蚀刻工艺以将第一蚀刻工艺形成为第一所需宽度，同时执行第二蚀刻工艺以形成另一间隔物结构至第二所需宽度。

公开(公告)号：US5429976A

公开(公告)日：1995-07-04

申请号：US158787

申请日：1993-12-01

Applicant: Gary Hong ,  Cheng-Han Huang

Inventor： Gary Hong ,  Cheng-Han Huang

IPC: H01L21/02 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC classification number: H01L28/40 ,  H01L27/10808

Abstract: A method is described for forming a dynamic random access memory cell capacitor in which polysilicon word lines are formed in a self-aligned method on top of the gate electrodes of the memory cell wherein the polysilicon word lines act to increase the surface area and hence to increase the capacitance of the capacitor.

Abstract translation: 描述了一种用于形成动态随机存取存储单元电容器的方法，其中多晶硅字线以自对准方法形成在存储单元的栅电极之上，其中多晶硅字线用于增加表面积，因此， 增加电容的电容。

公开(公告)号：US5418176A

公开(公告)日：1995-05-23

申请号：US197748

申请日：1994-02-17

Applicant: Ming-Tzong Yang ,  Cheng-Han Huang ,  Chen-Chiu Hsue

Inventor： Ming-Tzong Yang ,  Cheng-Han Huang ,  Chen-Chiu Hsue

IPC: H01L21/8246

CPC classification number: H01L27/1122

Abstract: A process of fabricating a read only memory device (ROM) wherein the buried N+lines have desirable well defined very narrow widths and are closely spaced. In the process, an insulating layer is deposited on the substrate. Openings for the buried N+lines having vertical sidewalls are formed through the insulating layer. Spacer layers are formed on the vertical sidewalls of the openings. Impurities are implanted through the openings. The insulating layers is removed and the substrate is oxidized to form silicon oxide insulation strips over the buried N+implanted regions. Next, the read only memory (ROM) device is completed by fabricating floating gates and overlying control gates between the buried N+lines interconnected by a conductive lines that are orthogonal to the buried N+buried lines.

Abstract translation: 一种制造只读存储器件（ROM）的工艺，其中掩埋的N +线具有期望的良好定义非常窄的宽度并且紧密间隔开。 在该过程中，绝缘层沉积在衬底上。 通过绝缘层形成具有垂直侧壁的埋入N +线的开口。 间隔层形成在开口的垂直侧壁上。 通过开口植入杂质。 绝缘层被去除并且衬底被氧化以在掩埋的N +注入区域上形成氧化硅绝缘条。 接下来，通过在与埋置的N +掩埋线正交的导线相互连接的掩埋N +线之间制造浮动栅极和覆盖控制栅极来完成只读存储器（ROM）器件。

公开(公告)号：US08604846B2

公开(公告)日：2013-12-10

申请号：US13295270

申请日：2011-11-14

Applicant: Hsiao-Chung Cheng ,  Cheng-Han Huang ,  Meng-Sheng Chang

Inventor： Hsiao-Chung Cheng ,  Cheng-Han Huang ,  Meng-Sheng Chang

IPC: H03L7/00

CPC classification number: G11C19/28

Abstract: An exemplary resetting circuit adapted for regulating a voltage on an output terminal of a shift register is disclosed. The resetting circuit includes a reset driving module and a reset module. The reset driving module is received with an enable signal to output a control voltage signal to an output terminal of the reset driving module. The reset module is electrically coupled to the output terminal of the shift register and the output terminal of the reset circuit driving module, and is controlled by the control voltage signal on the output terminal of the reset driving module to determine whether switching on an electrical path between the output terminal of the shift register and a gate-off voltage level.

Abstract translation: 公开了一种适于调节移位寄存器的输出端上的电压的示例性复位电路。 复位电路包括复位驱动模块和复位模块。 复位驱动模块被接收有使能信号，以将控制电压信号输出到复位驱动模块的输出端子。 复位模块电耦合到移位寄存器的输出端和复位电路驱动模块的输出端，并由复位驱动模块的输出端上的控制电压信号控制，以确定是否接通电路 在移位寄存器的输出端子与栅极截止电压电平之间。