公开(公告)号：US06432768B1

公开(公告)日：2002-08-13

申请号：US09510970

申请日：2000-02-21

申请人： Sun-Chieh Chien ,  Der-Yuan Wu

发明人： Sun-Chieh Chien ,  Der-Yuan Wu

IPC分类号： H01L218242

CPC分类号： H01L27/10894 ,  H01L27/10873 ,  H01L29/665

摘要： A method of fabricating a memory device and a logic device on the same chip is described, wherein the memory device has a first gate on a first region of the chip, and wherein the logic device has a second gate with a sidewall on a second region of the chip. A conductive layer and a first suicide layer are sequentially formed over the first and the second regions of the chip. Over the first region of the chip, the first silicide layer and the conductive layer are patterned to form the first gate. Ions are first implanted into the first region of the chip, by using the first gate as a mask, to form a first doped region. A dielectric layer is formed to cap the first gate, the first doped region and the first region of the chip. The first silicide layer over the second region of the chip is removed. Over the second region of the chip, the conductive layer is patterned to form the second gate. Ions are second implanted into the second region of the chip, by using the second gate as a mask, to form a second doped region.

摘要翻译： 描述了在同一芯片上制造存储器件和逻辑器件的方法，其中存储器件在芯片的第一区域上具有第一栅极，并且其中逻辑器件具有在第二区域上具有侧壁的第二栅极 的芯片。 在芯片的第一和第二区域上依次形成导电层和第一硅化物层。 在芯片的第一区域上，第一硅化物层和导电层被图案化以形成第一栅极。 通过使用第一栅极作为掩模，首先将离子注入到芯片的第一区域中，以形成第一掺杂区域。 形成介电层，以覆盖芯片的第一栅极，第一掺杂区域和第一区域。 去除芯片第二区域上的第一硅化物层。 在芯片的第二区域上，对导电层进行图案化以形成第二栅极。 通过使用第二栅极作为掩模，将第二注入到芯片的第二区域中，以形成第二掺杂区域。

公开(公告)号：US6103606A

公开(公告)日：2000-08-15

申请号：US727089

申请日：1996-10-07

申请人： Der-Yuan Wu ,  Yi-Chung Sheng

发明人： Der-Yuan Wu ,  Yi-Chung Sheng

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L21/3205 ,  H01L21/44 ,  H01L23/48 ,  H01L27/108

CPC分类号： H01L21/28061 ,  H01L21/76886

摘要： On a substrate with a number rows of gates are formed. After a metal silicide layer is formed above the gates, a silicon-rich layer is formed. The silicon-rich layer is either a further metal silicide layer, with a higher silicon concentration or a pure silicon layer.

摘要翻译： 在具有数排栅极的衬底上形成。 在栅极之上形成金属硅化物层之后，形成富硅层。 富硅层是另一金属硅化物层，具有较高的硅浓度或纯硅层。

公开(公告)号：US6040231A

公开(公告)日：2000-03-21

申请号：US055684

申请日：1998-04-06

申请人： Der-Yuan Wu

发明人： Der-Yuan Wu

IPC分类号： H01L21/60 ,  H01L21/762 ,  H01L21/76 ,  H01L21/311

CPC分类号： H01L21/76232 ,  H01L21/76897

摘要： A method of forming a shallow trench isolation structure is disclosed. The method comprises providing a substrate; forming a first oxide layer, a stop layer and a second oxide layer successively on the substrate; patterning the second oxide layer, the stop layer and the first oxide layer and a portion of the substrate to form a trench wherein the trench has a top corner. Then, a recess is formed at the periphery of the pad oxide layer, using the salicide process to form an aslope periphery at the top corner. Consequently, kink effect is improved, leakage current is reduced and the performance of the device is enhanced.

摘要翻译： 公开了形成浅沟槽隔离结构的方法。 该方法包括提供基底; 在基板上依次形成第一氧化物层，停止层和第二氧化物层; 图案化第二氧化物层，停止层和第一氧化物层以及衬底的一部分以形成沟槽，其中沟槽具有顶角。 然后，使用自对准硅化物工艺在顶部角部处形成斜边周边，在衬垫氧化物层的周围形成凹部。 因此，扭结效应得到改善，泄漏电流降低，器件的性能提高。

公开(公告)号：US6030867A

公开(公告)日：2000-02-29

申请号：US975708

申请日：1997-11-21

申请人： Sun-Chieh Chien ,  Jason Jenq ,  Der-Yuan Wu ,  Chia-Wen Liang

发明人： Sun-Chieh Chien ,  Jason Jenq ,  Der-Yuan Wu ,  Chia-Wen Liang

IPC分类号： H01L21/02 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242

CPC分类号： H01L24/11 ,  H01L27/10852 ,  H01L28/84 ,  H01L21/76895 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105

摘要： The DRAM cell is formed by covering the cell's transfer FET with a conformal insulating layer. A self aligned contact etch removes a portion of the conformal insulating layer from above a first source/drain region of the FET and then a first polysilicon layer is deposited over the device. Etching defines a polysilicon pad from the first polysilicon layer with edges of the polysilicon pad disposed over the gate electrode and an adjacent wiring line. A thick, planarized second insulating layer is provided over the device, filling the volume defined by the locally cupped surface of the polysilicon pad. Etching is performed to remove a portion of the planarized insulating layer using the pad polysilicon layer as an etch stop for the process. A second, thick polysilicon layer is next provided to fill the cavity and the layer is patterned to laterally define the lower capacitor electrode. Hemispherical grained silicon (HSG-Si) is deposited on the surface of the patterned polysilicon layer and an etch back process is used to transfer the topology of the HSG-Si layer to the underlying polysilicon. Further processing provides a capacitor dielectric and an upper electrode.

摘要翻译： 通过用保形绝缘层覆盖电池的转移FET来形成DRAM单元。 自对准接触蚀刻从FET的第一源极/漏极区上方去除保形绝缘层的一部分，然后在器件上沉积第一多晶硅层。 蚀刻定义了来自第一多晶硅层的多晶硅焊盘，其中多晶硅焊盘的边缘设置在栅电极和相邻布线之上。 在该器件上方提供厚的平坦化的第二绝缘层，填充由多晶硅垫的局部杯形表面限定的体积。 使用焊盘多晶硅层作为该工艺的蚀刻停止来执行蚀刻以去除平坦化绝缘层的一部分。 接下来提供第二厚的多晶硅层以填充空腔，并且对该层进行图案化以横向限定下部电容器电极。 半球形晶粒硅（HSG-Si）沉积在图案化的多晶硅层的表面上，并且使用回蚀工艺将HSG-Si层的拓扑转移到下面的多晶硅。 进一步的处理提供电容器电介质和上电极。

公开(公告)号：US6017799A

公开(公告)日：2000-01-25

申请号：US40553

申请日：1998-03-18

申请人： Sun-Chieh Chien ,  Peter Hsue ,  Der-Yuan Wu

发明人： Sun-Chieh Chien ,  Peter Hsue ,  Der-Yuan Wu

IPC分类号： H01L21/8242 ,  H01L21/336

CPC分类号： H01L27/10894

摘要： A method of fabricating a dynamic random memory. On a semiconductor substrate comprising a memory cell region and a periphery circuit region, a first field implantation and a first anti-punch through implantation are performed. Using a photo-resist layer formed to cover the memory cell region as a mask, the periphery circuit region is performed with a second field implantation and a second anti-punch through implantation.

摘要翻译： 一种制造动态随机存储器的方法。 在包括存储单元区域和外围电路区域的半导体衬底上，执行第一场注入和第一抗穿透注入。 使用形成为覆盖存储单元区域作为掩模的光致抗蚀剂层，通过第二场注入和第二抗穿透注入来执行外围电路区域。

公开(公告)号：US06004845A

公开(公告)日：1999-12-21

申请号：US111306

申请日：1998-07-07

申请人： Benjamin Szu-Min Lin ,  Der-Yuan Wu

发明人： Benjamin Szu-Min Lin ,  Der-Yuan Wu

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： A method for fabricating crown-shaped a capacitor is provided. The method is comprised of the following steps. First, a dielectric layer is formed on a substrate having a pre-formed field effect transistor, then a contact hole which exposes one of the source/drain regions of the field effect transistor is defined and formed. Then a first conductive layer is formed in the contact hole and on the dielectric layer, a crown-shaped photoresist layer is formed by employing a mask comprising a transmission layer, a partial transmission layer, and a non-transmission layer. Next, the pattern on the photoresist layer is transferred onto the first conductive layer to form a crown-shaped conductive layer. Then, a dielectric film is formed on the top of the crown-shaped conductive layer, and a second conductive layer on the top of the dielectric film.

摘要翻译： 提供一种用于制造冠状电容器的方法。 该方法包括以下步骤。 首先，在具有预形成的场效应晶体管的基板上形成电介质层，然后形成露出场效应晶体管的源/漏区之一的接触孔。 然后在接触孔和电介质层上形成第一导电层，通过采用包括透射层，部分透射层和非透射层的掩模形成冠状光致抗蚀剂层。 接下来，将光致抗蚀剂层上的图案转印到第一导电层上以形成冠状导电层。 然后，在冠状导电层的顶部形成电介质膜，在电介质膜的顶部形成第二导电层。

公开(公告)号：US5795805A

公开(公告)日：1998-08-18

申请号：US904543

申请日：1997-08-04

申请人： Der-Yuan Wu ,  Jason Jenq

发明人： Der-Yuan Wu ,  Jason Jenq

IPC分类号： H01L21/8242

CPC分类号： H01L27/10852

摘要： A fabricating method of a dynamic random access memory is provided. The characteristic of the method is the formation of a dielectric layer to protect a polysilicon layer of hemispheric grains, and thus, the slurry residue from chemical-mechanical polishing process is avoided. In addition, the dielectric layer and the oxide layer can be removed by the same step of wet etching without an additional process. The exposure limitation is not restricted by the shrinkage of the devices. Therefore, the polysilicon layer of hemispherical grains can be removed precisely as expected.

摘要翻译： 提供了一种动态随机存取存储器的制造方法。 该方法的特征在于形成介电层以保护半球晶粒的多晶硅层，从而避免了化学机械抛光过程中的残留物。 此外，可以通过相同的湿法蚀刻步骤除去电介质层和氧化物层，而无需额外的工艺。 曝光限制不受设备收缩的限制。 因此，半球形晶粒的多晶硅层可以按预期精确地去除。

公开(公告)号：US5739046A

公开(公告)日：1998-04-14

申请号：US657058

申请日：1996-05-28

申请人： Water Lur ,  Shih-Chanh Chang ,  Jiun Yuan Wu ,  Der Yuan Wu

发明人： Water Lur ,  Shih-Chanh Chang ,  Jiun Yuan Wu ,  Der Yuan Wu

IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76864 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76856

摘要： A new method of forming a metal diffusion barrier layer is described. Semiconductor device structures are formed in and on a semiconductor substrate. At least one dielectric layer covers the semiconductor structures and at least one contact hole has been opened through the dielectric layer(s) to the semiconductor substrate. A metal diffusion barrier layer is now formed using the following steps: In the first step, a thin layer of titanium is deposited conformally over the surface of the dielectric layer(s) and within the contact opening(s) and annealed in a nitrogen atmosphere at a temperature of between about 580.degree. to 630.degree. C. for between about 20 to 120 seconds. The second step is to form stable and adhesive titanium compounds on the pre-metal dielectric layer as well as to form a low resistance silicide on the contact silicon by annealing at between about 800.degree. to 900.degree. C. for between about 5 to 60 seconds. The final step is to release the system stress by tempering the layer at a temperature of between about 600.degree. to 750.degree. C. This completes the barrier layer which has good adhesion to the dielectric layer(s) and, therefore, promotes improved pad bonding yield.

摘要翻译： 描述形成金属扩散阻挡层的新方法。 在半导体衬底中形成半导体器件结构。 至少一个电介质层覆盖半导体结构，并且至少一个接触孔已经通过介电层被打开到半导体衬底。 现在通过以下步骤形成金属扩散阻挡层：在第一步骤中，将薄的钛层保形地沉积在电介质层的表面和接触开口内，并在氮气气氛中退火 在约580℃至630℃之间的温度下进行约20至120秒。 第二步是在金属前介电层上形成稳定且粘合的钛化合物，并在接触硅上形成低电阻硅化物，在约800-900℃之间退火约5至60秒 。 最后一步是通过在约600至750℃的温度下回火层来释放系统应力。这完成了与电介质层具有良好粘附性的阻挡层，因此促进改进的焊盘接合 产量。

公开(公告)号：US5703408A

公开(公告)日：1997-12-30

申请号：US419558

申请日：1995-04-10

申请人： Liu Ming-Tsung ,  Bill Y. B. Hsu ,  Hsien-Dar Chung ,  Der-Yuan Wu

发明人： Liu Ming-Tsung ,  Bill Y. B. Hsu ,  Hsien-Dar Chung ,  Der-Yuan Wu

IPC分类号： H01L23/485 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L2224/02166 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15787 ,  Y10T29/49124 ,  Y10T29/49155 ,  Y10T29/49204

摘要： A structure and a process for forming an improved bonding pad which allows better bonding between a bond wire and a metal bonding pad. Stripes are formed on a substrate. A conformal dielectric layer, a conformal barrier layer and a metal layer are formed over the stripes. A passivation layer with a window is formed defining a bonding pad area. The stripes promote an irregular surface in the barrier and metal layers which reduce stress between the dielectric layer, the barrier layer and the metal layer. Also, the irregular surfaces increase the barrier metal adhesion to the dielectric layer, reduce bond pad peel off, and increase bonding yields.

摘要翻译： 一种用于形成改进的接合焊盘的结构和工艺，其允许接合线和金属接合焊盘之间的更好的接合。 条纹形成在基板上。 在条纹上形成保形电介质层，保形阻挡层和金属层。 形成具有窗口的钝化层，限定了焊盘区域。 条纹促进阻挡层和金属层中的不规则表面，其减小介电层，阻挡层和金属层之间的应力。 此外，不规则表面增加了对电介质层的阻挡金属粘附性，减少了接合焊盘剥离，并增加了粘合产率。

公开(公告)号：US5599746A

公开(公告)日：1997-02-04

申请号：US239229

申请日：1994-05-06

申请人： Water Lur ,  Der-Yuan Wu

发明人： Water Lur ,  Der-Yuan Wu

IPC分类号： H01L21/301 ,  H01L21/768 ,  H01L21/28

CPC分类号： H01L21/76889 ,  Y10S438/964

摘要： A method for eliminating the peeling of polycide at the edge of a wafer used to fabricate semi-conductors and integrated circuits. A global rough surface is formed on the wafer. The rough surface on the substrate wafer releases most of the thermal stress between the silicide and polysilicon layers which are found in conventional devices. A "peel free" surface results and the particle problem is lessened.

摘要翻译： 一种用于消除在用于制造半导体和集成电路的晶片的边缘处的多晶硅化合物的剥离的方法。 在晶片上形成全局粗糙表面。 衬底晶圆上的粗糙表面释放了常规器件中发现的硅化物和多晶硅层之间的大部分热应力。 “剥离”表面结果，粒子问题减弱。