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    Device and method for etching flash memory gate stacks comprising high-k dielectric
    4.
    发明授权
    Device and method for etching flash memory gate stacks comprising high-k dielectric 有权
    用于蚀刻包括高k电介质的闪存存储器栅极堆叠的器件和方法

    公开(公告)号：US07780862B2

    公开(公告)日：2010-08-24

    申请号：US11386054

    申请日：2006-03-21

    申请人： Meihua Shen ,  Xikun Wang ,  Wei Liu ,  Yan Du ,  Shashank Deshmukh

    发明人： Meihua Shen ,  Xikun Wang ,  Wei Liu ,  Yan Du ,  Shashank Deshmukh

    IPC分类号： H01L21/302

    CPC分类号： H01L21/32136 ,  H01L21/31116

    摘要： In one implementation, a method is provided capable of etching a wafer to form devices including a high-k dielectric layer. The method includes etching an upper conductive material layer in a first plasma chamber with a low cathode temperature, transferring the wafer to a second chamber without breaking vacuum, etching a high-k dielectric layer in the second chamber, and transferring the wafer from the second chamber to the first plasma chamber without breaking vacuum. A lower conductive material layer is etched with a low cathode temperature in the first chamber. In one implementation, the high-k dielectric etch is a plasma etch using a high temperature cathode. In another implementation, the high-k dielectric etch is a reactive ion etch.

    摘要翻译： 在一个实施方式中，提供了能够蚀刻晶片以形成包括高k电介质层的器件的方法。 该方法包括在具有低阴极温度的第一等离子体室中蚀刻上导电材料层，将晶片转移到第二室而不破坏真空，蚀刻第二室中的高k电介质层，以及从第二室转移晶片 室到第一等离子体室，而不破坏真空。 在第一室中以低阴极温度蚀刻下导电材料层。 在一个实施方案中，高k电介质蚀刻是使用高温阴极的等离子体蚀刻。 在另一个实施方案中，高k电介质蚀刻是反应离子蚀刻。

    METHODS OF TRIMMING AMORPHOUS CARBON FILM FOR FORMING ULTRA THIN STRUCTURES ON A SUBSTRATE
    5.
    发明申请
    METHODS OF TRIMMING AMORPHOUS CARBON FILM FOR FORMING ULTRA THIN STRUCTURES ON A SUBSTRATE 审中-公开
    用于形成基底上超薄结构的非晶碳膜的方法

    公开(公告)号：US20090004875A1

    公开(公告)日：2009-01-01

    申请号：US12163888

    申请日：2008-06-27

    申请人： Meihua Shen ,  Diana Xiaobing Ma ,  Wendy H. Yeh ,  Kenneth MacWilliams ,  Wei Liu ,  Thorsten B. Lill

    发明人： Meihua Shen ,  Diana Xiaobing Ma ,  Wendy H. Yeh ,  Kenneth MacWilliams ,  Wei Liu ,  Thorsten B. Lill

    IPC分类号： H01L21/308

    CPC分类号： H01L21/0337

    摘要： Methods for forming an ultra thin structure using a method that includes trimming a mask layer during an etching process are provided. The embodiments described herein may be advantageously utilized to fabricate a submicron structure on a substrate having a critical dimension less than 55 nm and beyond. In one embodiment, a method of forming a submicron structure on a substrate may include providing a substrate having a patterned photoresist layer disposed on a film stack into an etch chamber, wherein the film stack includes at least a hardmask layer disposed on an underlying layer, trimming the photoresist layer to a first predetermined critical dimension, etching the hardmask layer through openings defined by the trimmed photoresist layer, trimming the hardmask layer to a second predetermined critical dimension, and etching the underlying layer through openings defined by the trimmed hardmask layer.

    摘要翻译： 提供了使用包括在蚀刻处理期间修整掩模层的方法来形成超薄结构的方法。 本文描述的实施例可有利地用于在临界尺寸小于55nm及以上的衬底上制造亚微米结构。 在一个实施例中，在衬底上形成亚微米结构的方法可以包括提供具有设置在膜堆叠上的图案化光致抗蚀剂层进入蚀刻室的衬底，其中所述膜堆叠包括至少设置在下层上的硬掩模层， 将光致抗蚀剂层修剪到第一预定临界尺寸，通过由修剪的光致抗蚀剂层限定的开口蚀刻硬掩模层，将硬掩模层修剪到第二预定临界尺寸，以及通过由修剪的硬掩模层限定的开孔蚀刻下层。

    DEVICE AND METHOD FOR ETCHING FLASH MEMORY GATE STACKS COMPRISING HIGH-K DIELECTRIC
    7.
    发明申请
    DEVICE AND METHOD FOR ETCHING FLASH MEMORY GATE STACKS COMPRISING HIGH-K DIELECTRIC 审中-公开
    用于蚀刻包含高K电介质的闪存存储器栅极堆叠的装置和方法

    公开(公告)号：US20080011423A1

    公开(公告)日：2008-01-17

    申请号：US11777714

    申请日：2007-07-13

    申请人： MEIHUA SHEN ,  Xikun Wang ,  Wei Liu ,  Yan Du ,  Shashank Deshmukh

    发明人： MEIHUA SHEN ,  Xikun Wang ,  Wei Liu ,  Yan Du ,  Shashank Deshmukh

    IPC分类号： C23F1/00

    CPC分类号： H01L21/32136 ,  H01L21/31116

    摘要： In one implementation, a method for etching a flash memory high-k gate stack on a workpiece is provided which includes etching a conductive material layer in a low temperature plasma chamber and etching a high-k dielectric layer in a high temperature plasma chamber. The workpiece is transferred between the low temperature plasma chamber and the high temperature plasma chamber through a vacuum transfer chamber connecting the low temperature plasma chamber and the high temperature plasma chamber. In one embodiment, an integrated etch station for etching a high-k flash memory structure is provided, which includes an etch chamber configured for plasma etch processing of a conductive material layer connected via a transfer chamber to an etch chamber configured for plasma etch processing of a high-k dielectric layer.

    摘要翻译： 在一个实施方案中，提供了一种用于蚀刻工件上的闪存高k栅极堆叠的方法，其包括在低温等离子体室中蚀刻导电材料层并蚀刻高温等离子体室中的高k电介质层。 工件通过连接低温等离子体室和高温等离子体室的真空传送室在低温等离子体室和高温等离子体室之间传递。 在一个实施例中，提供了用于蚀刻高k闪速存储器结构的集成蚀刻站，其包括蚀刻室，其被配置用于经由传送室连接到导电材料层的等离子体蚀刻处理到蚀刻室，所述蚀刻室被配置用于等离子体蚀刻处理 高k电介质层。

    ETCHING OF SiO2 WITH HIGH SELECTIVITY TO Si3N4 AND ETCHING METAL OXIDES WITH HIGH SELECTIVITY TO SiO2 AT ELEVATED TEMPERATURES WITH BCl3 BASED ETCH CHEMISTRIES
    8.
    发明申请
    ETCHING OF SiO2 WITH HIGH SELECTIVITY TO Si3N4 AND ETCHING METAL OXIDES WITH HIGH SELECTIVITY TO SiO2 AT ELEVATED TEMPERATURES WITH BCl3 BASED ETCH CHEMISTRIES 有权
    对具有高选择性的Si 3 N 4的SiO 2和具有高选择性的金属氧化物的蚀刻在基于BCl3的蚀刻化学的高温下

    公开(公告)号：US20070249182A1

    公开(公告)日：2007-10-25

    申请号：US11736562

    申请日：2007-04-17

    申请人： Radhika Mani ,  Nicolas Gani ,  Wei Liu ,  Meihua Shen ,  Shashank C. Deshmukh

    发明人： Radhika Mani ,  Nicolas Gani ,  Wei Liu ,  Meihua Shen ,  Shashank C. Deshmukh

    IPC分类号： H01L21/302 ,  H01L21/31

    CPC分类号： H01L21/31116 ,  H01L21/31122 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

    摘要： Wafers having a high K dielectric layer and an oxide or nitride containing layer are etched in an inductively coupled plasma processing chamber by applying a source power to generate an inductively coupled plasma, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be between 100° C. and 350° C., and etching the wafer with a selectivity of high K dielectric to oxide or nitride greater than 10:1. Wafers having an oxide layer and a nitride layer are etched in a reactive ion etch processing chamber by applying a bias power to the wafer, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be between 20° C. and 200° C., and etching the wafer with an oxide to nitride selectivity greater than 10:1. Wafers having an oxide layer and a nitride layer are etched in a an inductively coupled plasma processing chamber by applying a bias power to the wafer, applying a source power to generate an inductively coupled plasma, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be between 20° C. and 200° C., and etching the wafer with an oxide to nitride selectivity greater than 10:1.

    摘要翻译： 具有高K电介质层和含氧化物或氮化物的层的晶片在电感耦合等离子体处理室中被蚀刻，通过施加源功率以产生电感耦合等离子体，将包含BCl 3 >，将晶片的温度设置在100℃和350℃之间，并且以大于10:1的氧化物或氮化物的高K电介质的选择性蚀刻晶片。 具有氧化物层和氮化物层的晶片通过向晶片施加偏置功率而在反应离子蚀刻处理室中进行蚀刻，将包含BCl 3 3的气体引入室中，设定晶片的温度 在20℃和200℃之间，并且以大于10:1的氧化物至氮化物选择性蚀刻晶片。 在电感耦合等离子体处理室中蚀刻具有氧化物层和氮化物层的晶片，通过向晶片施加偏置功率，施加源电力以产生电感耦合等离子体，将包括BCI 3，将晶片的温度设定在20℃至200℃之间，并以大于10:1的氧化物至氮化物选择性蚀刻晶片。

    Integration of silicon etch and chamber cleaning processes
    9.
    发明授权
    Integration of silicon etch and chamber cleaning processes 失效
    硅蚀刻和室清洁工艺的集成

    公开(公告)号：US06566270B1

    公开(公告)日：2003-05-20

    申请号：US09662677

    申请日：2000-09-15

    申请人： Wei Liu ,  Scott Williams ,  Stephen Yuen ,  David Mui ,  Meihua Shen

    发明人： Wei Liu ,  Scott Williams ,  Stephen Yuen ,  David Mui ,  Meihua Shen

    IPC分类号： H01L21302

    CPC分类号： H01L21/3065

    摘要： A method for processing a substrate disposed in a substrate process chamber having a source power includes transferring the substrate into the substrate process chamber. A trench is etched on the substrate by exposing the substrate to a plasma formed from a first etchant gas by applying RF energy from the source power system and biasing the plasma toward the substrate. Byproducts adhering to inner surfaces of the substrate process chamber are removed by igniting a plasma formed from a second etchant gas including a halogen source in the substrate process chamber without applying bias power or applying minimal bias power. Thereafter, the substrate is removed from the chamber. At least 100 more substrates are processed with the etching-a-trench step and removing-etch-byproducts step before performing a dry clean or wet clean operation on the chamber.

    摘要翻译： 用于处理设置在具有源功率的基板处理室中的基板的方法包括将基板转移到基板处理室中。 通过从源功率系统施加RF能量并将等离子体偏压到衬底，将衬底暴露于由第一蚀刻剂气体形成的等离子体上，在衬底上蚀刻沟槽。 通过在不施加偏置功率或施加最小偏压功率的情况下点燃由包括卤素源的第二蚀刻剂气体在衬底处理室中形成的等离子体而去除附着于衬底处理室的内表面的副产物。 此后，将基板从腔室中取出。 在对腔室进行干洗或湿清洁操作之前，至少用100个蚀刻a沟槽步骤和去除蚀刻副产物步骤处理多个衬底。

    Etch methods to form anisotropic features for high aspect ratio applications
    10.
    发明申请
    Etch methods to form anisotropic features for high aspect ratio applications 审中-公开
    蚀刻方法来形成高纵横比应用的各向异性特征

    公开(公告)号：US20070202700A1

    公开(公告)日：2007-08-30

    申请号：US11363789

    申请日：2006-02-27

    申请人： Uwe Leucke ,  Meihua Shen ,  Guangxiang Jin ,  Xikun Wang ,  Wei Liu ,  Scott Williams

    发明人： Uwe Leucke ,  Meihua Shen ,  Guangxiang Jin ,  Xikun Wang ,  Wei Liu ,  Scott Williams

    IPC分类号： H01L21/302 ,  C23F1/00

    CPC分类号： C23F4/00 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/32136 ,  H01L21/32137 ,  H01L21/32139

    摘要： Methods for forming anisotropic features for high aspect ratio application in etch process are provided in the present invention. The methods described herein advantageously facilitates profile and dimension control of features with high aspect ratios through a sidewall passivation management scheme. In one embodiment, sidewall passivations are managed by selectively forming an oxidation passivation layer on the sidewall and/or bottom of etched layers. In another embodiment, sidewall passivation is managed by periodically clearing the overburden redeposition layer to preserve an even and uniform passivation layer thereon. The even and uniform passivation allows the features with high aspect ratios to be incrementally etched in a manner that pertains a desired depth and vertical profile of critical dimension in both high and low feature density regions on the substrate without generating defects and/or overetching the underneath layers.

    摘要翻译： 在本发明中提供了用于在蚀刻工艺中形成用于高纵横比应用的各向异性特征的方法。 本文描述的方法通过侧壁钝化管理方案有利地促进具有高纵横比的特征的轮廓和尺寸控制。 在一个实施例中，通过在蚀刻层的侧壁和/或底部选择性地形成氧化钝化层来管理侧壁钝化。 在另一个实施例中，通过周期性地清除覆盖层再沉积层以在其上保持均匀且均匀的钝化层来管理侧壁钝化。 均匀和均匀的钝化允许以在衬底上的高和低特征密度区域中具有临界尺寸的期望深度和垂直分布的方式来逐渐蚀刻具有高纵横比的特征，而不产生缺陷和/或过蚀刻下面 层。