Digital filter system, carrier reproduction circuit using the digital
filter system, and demodulation circuit using the carrier reproduction
circuit
    1.
    发明授权
    Digital filter system, carrier reproduction circuit using the digital filter system, and demodulation circuit using the carrier reproduction circuit 失效
    数字滤波器系统,使用数字滤波器系统的载波再现电路和使用载波再现电路的解调电路

    公开(公告)号:US5999574A

    公开(公告)日:1999-12-07

    申请号:US814879

    申请日:1997-03-13

    IPC分类号: H04B1/30 H04L27/00 H04L27/14

    摘要: An input analog signal is sampled at a sampling frequency f.sub.s, which is four times a carrier frequency f.sub.c. A demultiplexer 11 outputs supplied data to four systems sequentially, and generates four zero carriers whose frequencies and amplitudes are equal to each other, with only the phases being different. The delay circuits 12 to 15 delay each one of the zero carriers, and supply delayed signals to adaptive filters 16 to 19. Data output from the four adaptive filters 16 to 19 are selected by a multiplexer 22, and the multiplexer 22 outputs the selected signals as a single signal. The difference between a first zero carrier and an output signals of the first adaptive filter 16 is obtained, and tap coefficients of the adaptive filters 16 to 19 are controlled in accordance with an LMS algorithm based on the difference. A signal output by the multiplexer 22 is output as a reproduced carrier.

    摘要翻译: 输入模拟信号以采样频率fs进行采样,采样频率fs是载波频率fc的四倍。 解复用器11将提供的数据顺序地输出到四个系统,并且产生四个零载波,其频率和幅度彼此相等,只有相位不同。 延迟电路12至15延迟零载波中的每一个,并将延迟的信号提供给自适应滤波器16至19.从多路复用器22选择从四个自适应滤波器16至19输出的数据,并且多路复用器22输出所选择的信号 作为单个信号。 获得第一自适应滤波器16的第一零载波和输出信号之间的差异,并且根据基于该差的LMS算法来控制自适应滤波器16至19的抽头系数。 由复用器22输出的信号作为再现载波输出。

    Digital filter system
    2.
    发明授权
    Digital filter system 失效
    数字滤波系统

    公开(公告)号:US5856934A

    公开(公告)日:1999-01-05

    申请号:US827407

    申请日:1997-03-27

    IPC分类号: H03H17/02 G06F17/10

    CPC分类号: H03H17/0294

    摘要: Constants {P.sub.b00i, Q.sub.b00j, . . . , P.sub.ak2i, Q.sub.ak2j, P.sub.ci, Q.sub.cj, P.sub.di, and Q.sub.dj } for calculating each of filter coefficients {a.sub.k1, a.sub.k2, b.sub.00, b.sub.k1, b.sub.k2, c and d} for a digital filter 15 by using non-linear polynomials for pass band position data x and pass band width data y are stored in a memory 13. The constants {P.sub.b00i, Q.sub.b00j, . . . , P.sub.ak2i, Q.sub.ak2j, P.sub.ci, Q.sub.cj, P.sub.di, and Q.sub.dj } are determined by using the least square method so that the sum of the square of the errors between the filter coefficients calculated by using non-liner polynomials and the filter coefficients of digital filter having known characteristics becomes the least or the minimum. A CPU 11 calculates the filter coefficients non-linearly by using the constants stored in the memory 13, and sets the results to the digital filter 15 when new pass band position data x or pass band width data y is input at knobs SC and SW.

    摘要翻译: 常数{Pb00i,Qb00j,。 。 。 ,Pak2i,Qak2j,Pci,Qcj,Pdi和Qdj},用于通过使用用于通带位置的非线性多项式来计算数字滤波器15的滤波器系数{ak1,ak2,b00,bk1,bk2,c和d} 数据x和通带宽度数据y存储在存储器13中。常数{Pb00i,Qb00j,..., 。 。 ,Pak2i,Qak2j,Pci,Qcj,Pdi和Qdj}通过使用最小二乘法确定,使得通过使用非线性多项式计算的滤波器系数与数字滤波器的滤波器系数之间的误差的平方和之和 已知特征变得最小或最小。 CPU 11通过使用存储在存储器13中的常数非线性地计算滤波器系数,并且当在通过旋钮SC和SW处输入新的通带位置数据x或通带宽度数据y时,将结果设置为数字滤波器15。

    Digital phase modulator formed with a fixed-point digital signal
processor
    3.
    发明授权
    Digital phase modulator formed with a fixed-point digital signal processor 失效
    数字相位调制器用定点数字信号处理器形成

    公开(公告)号:US5831488A

    公开(公告)日:1998-11-03

    申请号:US801728

    申请日:1996-06-27

    IPC分类号: H03H17/02 H03C3/00 H04L27/20

    CPC分类号: H04L27/2092

    摘要: Data from an A/D converter is supplied to a fixed-point DSP. The fixed-point DSP adjusts the level of the data x so that computed results do not exceed .+-.1. In succession, for the i-th data x.sub.i, the fixed-point DSP computes cos .pi..multidot.x.sub.i when i=1, 5, . . . , -sin .pi..multidot.x.sub.i when i=2, 6, . . . , -cos .pi..multidot.x.sub.i when i=3, 7, . . . and sin .pi..multidot.x.sub.i when i=4, 8, . . . and outputs a digital phase modulated signal y(t) by outputting the computed results in order. Trigonometrical functions are computed by expanding them to a series so that the intermediate computed results do not exceed .+-.1.

    摘要翻译: 来自A / D转换器的数据被提供给定点DSP。 定点DSP调整数据x的电平,以便计算结果不超过+/- 1。 接下来,对于第i个数据xi,当i = 1,5时,定点DSP计算cos pi xxi。 。 。 当i = 2,6时,-sin pi xxi。 。 。 ,当i = 3,7时,-cos pi xxi。 。 。 当i = 4,8时,sin pi xxi。 。 。 并且通过按顺序输出计算结果来输出数字相位调制信号y(t)。 通过将三角函数扩展为一系列来计算,以便中间计算结果不超过+/- 1。

    Maintaining linear beamforming weights in communications systems
    4.
    发明授权
    Maintaining linear beamforming weights in communications systems 有权
    在通信系统中维持线性波束成形权重

    公开(公告)号:US08755475B1

    公开(公告)日:2014-06-17

    申请号:US13411507

    申请日:2012-03-02

    摘要: Methods and systems that enhance interference cancellation in communication channels are described. Samples are obtained from stacked carriers in a received signal and a data vector is created from the samples. Stacked carriers are selected using a steering vector received during synchronization of the receiver. The steering vector is calculated to obtain cancellation of interference from another receiver and is calculated based on time domain channel estimation. Specialized time domain training sequences and simple cross correlation are used to obtain a channel estimate for use in stacked carrier beamforming and/or for use in OFDM based spatial beamforming. State space or filter-based modeled interpolators or whitening matrix-filters in the frequency or time domain are used for interpolation of the channels to maintain linear beamforming weights as a function of time or frequency. Space time adaptive processing facilitates beamforming of communications signals for OFDM and 802.16 (WiMax) systems.

    摘要翻译: 描述了在通信信道中增强干扰消除的方法和系统。 在接收信号中从堆叠载波获取样本,并从样本创建数据向量。 使用在接收机同步期间接收到的导向矢量来选择堆叠的载波。 计算导向矢量以获得来自另一接收机的干扰的抵消,并且基于时域信道估计来计算。 使用专用时域训练序列和简单的互相关来获得用于堆叠载波波束成形和/或用于基于OFDM的空间波束形成中的信道估计。 在频率或时域中的状态空间或基于滤波器的建模的内插器或白化矩阵滤波器被用于信道的插值,以维持作为时间或频率的函数的线性波束成形权重。 空时自适应处理有利于OFDM和802.16(WiMax)系统的通信信号的波束成形。

    Self-calibrating rate-adaptive pacemaker

    公开(公告)号:US08494632B2

    公开(公告)日:2013-07-23

    申请号:US13230563

    申请日:2011-09-12

    IPC分类号: A61N1/18

    CPC分类号: A61N1/365 A61N1/36585

    摘要: A system and method for automatically adjusting the operating parameters of a rate-adaptive cardiac pacemaker. In accordance with the method, maximum exertion levels attained by the patient are measured at periodic intervals and stored. The stored maximum exertion levels may then be used to update a long-term maximal exertion level, and the slope of the rate-response curve is adjusted to map the updated long-term maximal exertion level to a maximum allowable pacing rate. The stored maximum exertion levels may also be used to update a sensor target rate which is used to adjust the slope of the rate response curve.

    Adaptive anti-tachycardia therapy apparatus and method
    8.
    发明授权
    Adaptive anti-tachycardia therapy apparatus and method 有权
    适应性抗心动过速治疗仪及方法

    公开(公告)号:US07353060B2

    公开(公告)日:2008-04-01

    申请号:US10953081

    申请日:2004-09-29

    IPC分类号: A61N1/362

    CPC分类号: A61N1/3962

    摘要: A method and apparatus for delivering anti-tachycardia pacing in an adaptive manner is disclosed. A cardiac rhythm management device, such as an implantable pacemaker, having anti-tachycardia pacing capability delivers anti-tachycardia pacing therapy in accordance with a selected pacing protocol upon detection of a terminable arrhythmia. The protocol is selected from a library of available protocols. A record of the successes and failures of each available protocol in converting tachyarrhythmias is maintained in a result table for use in selecting the protocol.

    摘要翻译: 公开了以自适应方式递送抗心动过速起搏的方法和装置。 具有抗心动过速起搏能力的心脏节律管理装置,例如可植入心脏起搏器,在检测到可终止的心律失常时,根据选定的起搏方案提供抗心动过速起搏治疗。 协议从可用协议库中选择。 在用于选择协议的结果表中保留了每种可用协议在转换快速性心律失常方面的成功和失败的记录。

    Method and apparatus for adaptive tachycardia and fibrillation discrimination
    9.
    发明授权
    Method and apparatus for adaptive tachycardia and fibrillation discrimination 有权
    适应性心动过速和原纤维化鉴别的方法和装置

    公开(公告)号:US06230055B1

    公开(公告)日:2001-05-08

    申请号:US09378591

    申请日:1999-08-20

    IPC分类号: A61N137

    CPC分类号: A61N1/3622 A61N1/3962

    摘要: An implantable cardioverter/defibrillator with antitachycardia pacing capability and method for operating same in which the detection zone boundary used to discriminate between tachycardia and fibrillation is adaptively adjusted based upon operating experience. Rate zones are provided for further classifying detected episodes of tachycardia and fibrillation according to the certainty of their being correctly identified based upon past operating experience. Adjustments of the rate zones and the fibrillation detection zone boundary are made based upon the results of antitachycardia pacing in attempting to terminate arrhythmic episodes.

    摘要翻译: 一种具有抗心动过速起搏能力的植入式心律转复除颤器及其操作方法,其中基于操作经验自适应调整用于区分心动过速和颤动的检测区边界。 提供速率区,用于根据过去的操作经验正确识别检测到的心动过速和颤动发作进一步分类。 基于抗心律失常起搏试图终止心律失常发作的结果,进行速率区和原纤维化检测区边界的调整。

    Multi-stage detection system in digital demodulator
    10.
    发明授权
    Multi-stage detection system in digital demodulator 失效
    数字解调器多级检测系统

    公开(公告)号:US06181751B2

    公开(公告)日:2001-01-30

    申请号:US08953929

    申请日:1997-10-20

    申请人: Weimin Sun

    发明人: Weimin Sun

    IPC分类号: H03D100

    CPC分类号: H04L27/2331 H03D3/006

    摘要: A multi-stage detection system in a digital modulator includes a first-stage detector, a second-stage detector, and a third-stage detector. The first-stage detector detects an input signal. The second-stage detector receives the outputs from the first-stage detector. The third-stage detector receives the outputs from the second-stage detector. The first-stage detector includes first to third delays, first to third adders, and first to third detectors. The first delay delays the input signal by one sampling period. The first adder adds the input signal to the output from the first delay. The first detector detects the output from the first adder. The second delay delays the output from the first delay by one sampling period. The second adder adds the input signal to the output from the second delay. The second detector detects an output from the second adder. The third delay delays the output from the second delay by one sampling period. The third adder adds the input signal to the output from the third delay. The third detector detects the output from the third adder.

    摘要翻译: 数字调制器中的多级检测系统包括第一级检测器,第二级检测器和第三级检测器。 第一级检测器检测输入信号。 第二级检测器接收来自第一级检测器的输出。 第三级检测器接收来自第二级检测器的输出。 第一级检测器包括第一至第三延迟,第一至第三加法器和第一至第三检测器。 第一个延迟将输入信号延迟一个采样周期。 第一个加法器将输入信号从第一个延迟加到输出端。 第一检测器检测来自第一加法器的输出。 第二延迟将第一延迟的输出延迟一个采样周期。 第二加法器将输入信号从第二延迟加到输出端。 第二检测器检测来自第二加法器的输出。 第三个延迟将第二个延迟的输出延迟一个采样周期。 第三加法器将输入信号从第三延迟加到输出端。 第三检测器检测来自第三加法器的输出。