-
公开(公告)号：US20100314713A1
公开(公告)日：2010-12-16
申请号：US12516301
申请日：2009-03-18
CPC分类号： H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： An IC inductor structure is provided which includes a first inductor element formed on a semiconductor substrate and at least a second inductor element formed on the semiconductor substrate proximate the first inductor element. The first inductor element has a first effective magnetic field direction associated therewith, and the second inductor element has a second effective magnetic field direction associated therewith. The first and second inductor elements are oriented relative to one another so as to create a non-zero angle between the first and second effective magnetic field directions.
摘要翻译： 提供了一种IC电感器结构，其包括形成在半导体衬底上的第一电感器元件和形成在靠近第一电感器元件的半导体衬底上的至少第二电感器元件。 第一电感器元件具有与其相关联的第一有效磁场方向，并且第二电感器元件具有与其相关联的第二有效磁场方向。 第一和第二电感器元件相对于彼此定向，以便在第一和第二有效磁场方向之间产生非零角度。
-
公开(公告)号：US08143696B2
公开(公告)日：2012-03-27
申请号：US12516301
申请日：2009-03-18
IPC分类号： H01L27/08
CPC分类号： H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： An IC inductor structure is provided which includes a first inductor element formed on a semiconductor substrate and at least a second inductor element formed on the semiconductor substrate proximate the first inductor element. The first inductor element has a first effective magnetic field direction associated therewith, and the second inductor element has a second effective magnetic field direction associated therewith. The first and second inductor elements are oriented relative to one another so as to create a non-zero angle between the first and second effective magnetic field directions.
摘要翻译： 提供一种IC电感器结构，其包括形成在半导体衬底上的第一电感器元件和形成在靠近第一电感器元件的半导体衬底上的至少第二电感器元件。 第一电感器元件具有与其相关联的第一有效磁场方向，并且第二电感器元件具有与其相关联的第二有效磁场方向。 第一和第二电感器元件相对于彼此定向，以便在第一和第二有效磁场方向之间产生非零角度。
-
公开(公告)号：US07777538B2
公开(公告)日：2010-08-17
申请号：US11367964
申请日：2006-03-03
申请人： Christopher J. Abel , Weiwei Mao
发明人： Christopher J. Abel , Weiwei Mao
CPC分类号： H03K5/01
摘要： Methods and apparatus are provided for controlling at least one of a rise time and a fall time of a signal. A plurality of time shifted clock signals are generated; and a received data signal is sampled using a plurality of parallel data paths, where each of the data paths are controlled by a corresponding one of the plurality of time shifted clock signals. The plurality of time shifted clock signals can be generated, for example, by at least one delay element. The plurality of parallel data paths can be substantially identical and comprise, for example, at least one latch or at least one flip flop. Compensation can optionally be provided for variations in, for example, process corner, supply voltage, aging and operating temperature.
摘要翻译： 提供了用于控制信号的上升时间和下降时间中的至少一个的方法和装置。 产生多个时移信号; 并且使用多个并行数据路径对接收到的数据信号进行采样，其中每个数据路径由多个时移时钟信号中的相应一个控制。 多个时移时钟信号可以例如由至少一个延迟元件产生。 多个并行数据路径可以是基本相同的，并且包括例如至少一个锁存器或至少一个触发器。 补偿可以任选地用于例如过程拐角，电源电压，老化和工作温度的变化。
-
公开(公告)号：US20090219057A1
公开(公告)日：2009-09-03
申请号：US12038972
申请日：2008-02-28
申请人： Mingdeng Chen , Ari Valero-Lopez , Weiwei Mao
发明人： Mingdeng Chen , Ari Valero-Lopez , Weiwei Mao
IPC分类号： G11C27/02
CPC分类号： H04L25/06 , G11C27/024 , H04L7/0087
摘要： Various embodiments of the present invention provide systems and circuits that provide for out of band detection. As one example, an out of band detection circuit is disclosed that includes an input signal, a clock generation circuit, and a sampling circuit. The clock generation circuit receives the input signal and derives therefrom a sampling clock, and the sampling circuit is operable to sample the input signal at a time indicated by the sampling clock.
摘要翻译： 本发明的各种实施例提供了提供带外检测的系统和电路。 作为一个例子，公开了一种包括输入信号，时钟产生电路和采样电路的带外检测电路。 时钟生成电路接收输入信号并从其中导出采样时钟，并且采样电路可操作以在由采样时钟指示的时间采样输入信号。
-
5.发明授权Duty cycle distortion (DCD) jitter modeling, calibration and generation methods 有权占空比失真（DCD）抖动建模，校准和生成方法公开(公告)号：US08125259B2
公开(公告)日：2012-02-28
申请号：US11968942
申请日：2008-01-03
申请人： Xingdong Dai , Weiwei Mao , Max J. Olsen , Geoffrey Zhang
发明人： Xingdong Dai , Weiwei Mao , Max J. Olsen , Geoffrey Zhang
IPC分类号： H03K3/017
摘要： A method and system for modeling and calibrating duty cycle distortion (DCD) of a Serializer and Deserializer (SerDes) device, including first generating a clock DCD signal. Once the clock DCD signal is generated, it is calibrating based upon results obtained from a filtering process of the clock DCD signal. Once the clock DCD signal is calibrated, a data DCD signal is generated and calibrated based upon results obtained from a filtering process of the data DCD signal.
摘要翻译： 一种用于建模和校准串行器和解串器（SerDes）器件的占空比失真（DCD）的方法和系统，包括首先产生时钟DCD信号。 一旦产生时钟DCD信号，它就是根据从时钟DCD信号的滤波处理获得的结果进行校准。 一旦时钟DCD信号被校准，基于从数据DCD信号的滤波处理获得的结果来产生和校准数据DCD信号。
-
6.发明申请DUTY CYCLE DISTORTION (DCD) JITTER MODELING, CALIBRATION AND GENERATION METHODS 有权占空比失真（DCD）抖动建模，校准和生成方法公开(公告)号：US20090177457A1
公开(公告)日：2009-07-09
申请号：US11968942
申请日：2008-01-03
申请人： Xingdong Dai , Weiwei Mao , Max J. Olsen , Geoffrey Zhang
发明人： Xingdong Dai , Weiwei Mao , Max J. Olsen , Geoffrey Zhang
IPC分类号： G06G7/62
摘要： A method and system for modeling and calibrating duty cycle distortion (DCD) of a Serializer and Deserializer (SerDes) device, including first generating a clock DCD signal. Once the clock DCD signal is generated, it is calibrating based upon results obtained from a filtering process of the clock DCD signal. Once the clock DCD signal is calibrated, a data DCD signal is generated and calibrated based upon results obtained from a filtering process of the data DCD signal.
摘要翻译： 一种用于建模和校准串行器和解串器（SerDes）器件的占空比失真（DCD）的方法和系统，包括首先产生时钟DCD信号。 一旦产生时钟DCD信号，它就是根据从时钟DCD信号的滤波处理获得的结果进行校准。 一旦时钟DCD信号被校准，基于从数据DCD信号的滤波处理获得的结果来产生和校准数据DCD信号。
-
公开(公告)号：US20070210832A1
公开(公告)日：2007-09-13
申请号：US11367964
申请日：2006-03-03
申请人： Christopher Abel , Weiwei Mao
发明人： Christopher Abel , Weiwei Mao
IPC分类号： H03K19/00
CPC分类号： H03K5/01
摘要： Methods and apparatus are provided for controlling at least one of a rise time and a fall time of a signal. A plurality of time shifted clock signals are generated; and a received data signal is sampled using a plurality of parallel data paths, where each of the data paths are controlled by a corresponding one of the plurality of time shifted clock signals. The plurality of time shifted clock signals can be generated, for example, by at least one delay element. The plurality of parallel data paths can be substantially identical and comprise, for example, at least one latch or at least one flip flop. Compensation can optionally be provided for variations in, for example, process corner, supply voltage, aging and operating temperature.
摘要翻译： 提供了用于控制信号的上升时间和下降时间中的至少一个的方法和装置。 产生多个时移信号; 并且使用多个并行数据路径对接收的数据信号进行采样，其中每个数据路径由多个时移时钟信号中的相应一个控制。 多个时移时钟信号可以例如由至少一个延迟元件产生。 多个并行数据路径可以是基本相同的，并且包括例如至少一个锁存器或至少一个触发器。 补偿可以任选地用于例如过程拐角，电源电压，老化和工作温度的变化。
-
公开(公告)号：US08044688B2
公开(公告)日：2011-10-25
申请号：US12038972
申请日：2008-02-28
申请人： Mingdeng Chen , Ari Valero-Lopez , Weiwei Mao
发明人： Mingdeng Chen , Ari Valero-Lopez , Weiwei Mao
CPC分类号： H04L25/06 , G11C27/024 , H04L7/0087
摘要： Various embodiments of the present invention provide systems and circuits that provide for out of band detection. As one example, an out of band detection circuit is disclosed that includes an input signal, a clock generation circuit, and a sampling circuit. The clock generation circuit receives the input signal and derives therefrom a sampling clock, and the sampling circuit is operable to sample the input signal at a time indicated by the sampling clock.
摘要翻译： 本发明的各种实施例提供了提供带外检测的系统和电路。 作为一个例子，公开了一种包括输入信号，时钟产生电路和采样电路的带外检测电路。 时钟生成电路接收输入信号并从其中导出采样时钟，并且采样电路可操作以在由采样时钟指示的时间采样输入信号。
-
9.发明授权公开(公告)号：US07432746B2
公开(公告)日：2008-10-07
申请号：US11495882
申请日：2006-07-31
申请人： Weiwei Mao
发明人： Weiwei Mao
IPC分类号： H03B1/00
CPC分类号： H03K19/018528
摘要： A buffer for interfacing complementary input signals having first logical voltage levels to a circuit operating with second logical voltage levels includes first and second branches outputting first and second complementary output signals, respectively. Each branch includes a PMOS and an NMOS transistor connected in series with a voltage-swing adjusting transistor between a first supply voltage and a second supply voltage. Control terminals of the PMOS and NMOS transistors each receive one of the complementary input signals, and a control terminal of the first voltage-swing adjusting transistor receives a first bias voltage. When the complementary input signal has a first voltage level, the voltage-swing adjusting transistor operates in a linear region and when the first complementary input signal has a second voltage level, current through the voltage-swing adjusting transistor is shut-off. No current flows in either branch when the buffer is in a static state.
摘要翻译： 用于将具有第一逻辑电压电平的互补输入信号与与第二逻辑电压电平工作的电路接口的缓冲器包括分别输出第一和第二互补输出信号的第一和第二分支。 每个分支包括在第一电源电压和第二电源电压之间与电压摆幅调节晶体管串联连接的PMOS和NMOS晶体管。 PMOS和NMOS晶体管的控制端分别接收互补输入信号之一，第一电压摆幅调整晶体管的控制端接收第一偏置电压。 当互补输入信号具有第一电压电平时，电压摆幅调节晶体管工作在线性区域中，并且当第一互补输入信号具有第二电压电平时，切断通过电压摆幅调节晶体管的电流。 当缓冲区处于静态时，任何一个分支中没有电流流动。
-
公开(公告)号：US20080024177A1
公开(公告)日：2008-01-31
申请号：US11495882
申请日：2006-07-31
申请人： Weiwei Mao
发明人： Weiwei Mao
IPC分类号： H03B1/00
CPC分类号： H03K19/018528
摘要： A buffer for interfacing complementary input signals having first logical voltage levels to a circuit operating with second logical voltage levels includes first and second branches outputting first and second complementary output signals, respectively. Each branch includes a PMOS and an NMOS transistor connected in series with a voltage-swing adjusting transistor between a first supply voltage and a second supply voltage. Control terminals of the PMOS and NMOS transistors each receive one of the complementary input signals, and a control terminal of the first voltage-swing adjusting transistor receives a first bias voltage. When the complementary input signal has a first voltage level, the voltage-swing adjusting transistor operates in a linear region and when the first complementary input signal has a second voltage level, current through the voltage-swing adjusting transistor is shut-off. No current flows in either branch when the buffer is in a static state.
-
-
-
-
-
-
-
-
-
搜索结果
11 条记录 (耗时 0.021 秒)
