公开(公告)号：US06512710B1

公开(公告)日：2003-01-28

申请号：US10004636

申请日：2001-12-04

申请人： Wen-Jer Tsai ,  Lan Ting Huang ,  Nian-Kai Zous ,  Ta-Hui Wang

发明人： Wen-Jer Tsai ,  Lan Ting Huang ,  Nian-Kai Zous ,  Ta-Hui Wang

IPC分类号： G11C700

CPC分类号： G11C29/50016 ,  G11C8/08 ,  G11C16/04 ,  G11C29/50

摘要： A reliability test method for a non-volatile memory. A relation curve of gate voltage versus read current degradation rate is obtained. The read current degradation rate of an actual gate voltage is estimated. From the relation curve, an accelerated test gate voltage and a test time corresponding to the actual gate voltage are obtained. With the accelerated test gate voltage, the test is continuously performed within the test time. Afterward, a test result of the memory is then obtained and, by the result, it is judged whether the data is valid or not. If the data is right (retained), the memory can be guarantied to have an expected lifetime; if the data is wrong (lost), the memory is judged as fails to pass the lifetime test.

摘要翻译： 用于非易失性存储器的可靠性测试方法。 获得栅极电压与读取电流退化率的关系曲线。 估计实际栅极电压的读取电流劣化率。 从关系曲线可以得到与实际栅极电压对应的加速测试栅极电压和测试时间。 加速测试门电压，测试在测试时间内连续进行。 然后，获得存储器的测试结果，并且通过结果判断数据是否有效。 如果数据正确（保留），则可以保证存储器具有预期的使用寿命; 如果数据错误（丢失），则存储器被判定为无法通过寿命测试。

公开(公告)号：US06563752B2

公开(公告)日：2003-05-13

申请号：US09945289

申请日：2001-08-30

申请人： Wen-Jer Tsai ,  Nian-Kai Zous ,  Ta-Hui Wang

发明人： Wen-Jer Tsai ,  Nian-Kai Zous ,  Ta-Hui Wang

IPC分类号： G11C700

CPC分类号： G11C29/50004 ,  G11C16/04 ,  G11C29/50

摘要： A qualification test method for a non-volatile memory includes determining a relation curve between the programming voltage and the lifetime of the memory cell. A programming voltage with respect to the memory array within the expected lifetime is estimated. According to the relation curve, the accelerating test voltage and the test time period corresponding to the programming voltage operated in the expected lifetime are computed out. The test is performed for the test time period under the accelerating test voltage. All the memory cells at the programmed state are tested to see if the original programmed state still remains. If the programmed state remains, the memory array is judged to have the life period. If the programmed state does not remain, the memory array is judged to have no the life period.

摘要翻译： 用于非易失性存储器的资格测试方法包括确定编程电压与存储器单元的寿命之间的关系曲线。 估计在预期寿命期内相对于存储器阵列的编程电压。 根据该关系曲线计算加速试验电压和对应于在预期寿命中运行的编程电压的试验时间。 在加速测试电压下进行测试时间。 测试编程状态下的所有存储单元，以查看原始编程状态是否仍然保留。 如果编程状态保持不变，则判断存储器阵列具有使用寿命。 如果编程状态不存在，则判断存储器阵列没有寿命周期。

公开(公告)号：US06445614B1

公开(公告)日：2002-09-03

申请号：US09930745

申请日：2001-08-14

申请人： Wen-Jer Tsai ,  Nian-Kai Zous ,  Ta-Hui Wang

发明人： Wen-Jer Tsai ,  Nian-Kai Zous ,  Ta-Hui Wang

IPC分类号： G11C1606

CPC分类号： G11C29/50004 ,  G11C16/04 ,  G11C29/50 ,  G11C2029/1202

摘要： An accelerated test for a non-volatile memory. A threshold voltage variation standard for assessment is selected. A set of negative gate bias voltages is applied to the gate terminals of the non-volatile memory to conduct the accelerated testing and obtain a test result. A curve relating lifetime and negative gate bias voltage is derived from the test result. According to the threshold voltage variation standard, the lifetime of the non-volatile memory is found. A word line negative gate bias voltage generator is coupled to a word line driver to apply a set of negative gate bias voltages to the gate terminals of programmed memory cells and conduct an accelerated testing.

摘要翻译： 非易失性存储器的加速测试。 选择用于评估的阈值电压变化标准。 一组负栅极偏置电压施加到非易失性存储器的栅极端子，以进行加速测试并获得测试结果。 从测试结果得出相关寿命和负栅极偏置电压的曲线。 根据阈值电压变化标准，找到非易失性存储器的寿命。 字线负栅极偏置电压发生器耦合到字线驱动器以将一组负栅极偏置电压施加到编程的存储器单元的栅极端子并进行加速测试。

公开(公告)号：US07187590B2

公开(公告)日：2007-03-06

申请号：US10876255

申请日：2004-06-24

申请人： Nian-Kai Zous ,  Wen-Jer Tsai ,  Hung-Yueh Chen ,  Tao Cheng Lu

发明人： Nian-Kai Zous ,  Wen-Jer Tsai ,  Hung-Yueh Chen ,  Tao Cheng Lu

IPC分类号： G11C16/04

CPC分类号： G11C16/0466 ,  H01L29/7885 ,  H01L29/792

摘要： A process and a memory architecture for operating a charge trapping memory cell is provided. The method for operating the memory cell includes establishing a high threshold state in the memory cell by injecting negative charge into the charge trapping structure to set a high state threshold. The method includes using a self-converging biasing procedure to establish a low threshold state for the memory cell by reducing the negative charge in the charge trapping structure to set the threshold voltage for the cell to a low threshold state. The negative charge is reduced in the memory cell by applying a bias procedure including at least one bias pulse. The bias pulse balances charge flow into and out of the charge trapping layer to achieve self-convergence on a desired threshold level. Thereby, an over-erase condition is avoided.

摘要翻译： 提供了用于操作电荷捕获存储器单元的过程和存储器架构。 用于操作存储单元的方法包括通过将负电荷注入到电荷俘获结构中来建立高的阈值状态，以设置高状态阈值。 该方法包括使用自会聚偏移过程来通过减少电荷俘获结构中的负电荷来为存储器单元建立低阈值状态，以将电池的阈值电压设置为低阈值状态。 通过施加包括至少一个偏置脉冲的偏置过程，在存储单元中负电荷减小。 偏置脉冲平衡进入和离开电荷捕获层的电荷流，以在期望的阈值水平上实现自会聚。 从而避免了过度擦除的情况。

公开(公告)号：US20050237813A1

公开(公告)日：2005-10-27

申请号：US10876255

申请日：2004-06-24

申请人： Nian-Kai Zous ,  Wen-Jer Tsai ,  Hung-Yueh Chen ,  Tao-Cheng Lu

发明人： Nian-Kai Zous ,  Wen-Jer Tsai ,  Hung-Yueh Chen ,  Tao-Cheng Lu

IPC分类号： G11C16/04 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/0466 ,  H01L29/7885 ,  H01L29/792

摘要： A process and a memory architecture for operating a charge trapping memory cell is provided. The method for operating the memory cell includes establishing a high threshold state in the memory cell by injecting negative charge into the charge trapping structure to set a high state threshold. The method includes using a self-converging biasing procedure to establish a low threshold state for the memory cell by reducing the negative charge in the charge trapping structure to set the threshold voltage for the cell to a low threshold state. The negative charge is reduced in the memory cell by applying a bias procedure including at least one bias pulse. The bias pulse balances charge flow into and out of the charge trapping layer to achieve self-convergence on a desired threshold level. Thereby, an over-erase condition is avoided.

摘要翻译： 提供了用于操作电荷捕获存储器单元的过程和存储器架构。 用于操作存储单元的方法包括通过将负电荷注入到电荷俘获结构中来建立高的阈值状态，以设置高状态阈值。 该方法包括使用自会聚偏移过程来通过减少电荷俘获结构中的负电荷来为存储器单元建立低阈值状态，以将电池的阈值电压设置为低阈值状态。 通过施加包括至少一个偏置脉冲的偏置过程，在存储单元中负电荷减小。 偏置脉冲平衡进入和离开电荷捕获层的电荷流，以在期望的阈值水平上实现自会聚。 从而避免了过度擦除的情况。

公开(公告)号：US07643337B2

公开(公告)日：2010-01-05

申请号：US11826574

申请日：2007-07-17

申请人： Yung-Feng Lin ,  Nian-Kai Zous ,  I-Jen Huang ,  Yin-Jen Chen

发明人： Yung-Feng Lin ,  Nian-Kai Zous ,  I-Jen Huang ,  Yin-Jen Chen

IPC分类号： G11C7/00

CPC分类号： G11C11/5642 ,  G11C2211/5634

摘要： A multi-bit flash memory and a reading method thereof. Multiple reference memory cells for saving reserved data are provided to operate together with multiple data memory cells. Before the data memory cells are read, data stored in the reference memory cell is sensed based on a present reference current. Then, a value of a new reference current for reading the data memory cells is determined according to a difference between the sensed data and the reserved data.

摘要翻译： 一种多位闪存及其读取方法。 提供用于保存预留数据的多个参考存储器单元以与多个数据存储单元一起操作。 在读取数据存储单元之前，基于当前的参考电流感测存储在参考存储器单元中的数据。 然后，根据感测数据和保留数据之间的差异来确定读取数据存储单元的新参考电流的值。

公开(公告)号：US06720614B2

公开(公告)日：2004-04-13

申请号：US10005270

申请日：2001-12-04

申请人： Hung-Sui Lin ,  Nian-Kai Zous ,  Han-Chao Lai ,  Tao-Cheng Lu

发明人： Hung-Sui Lin ,  Nian-Kai Zous ,  Han-Chao Lai ,  Tao-Cheng Lu

IPC分类号： H01L29788

CPC分类号： G11C16/0475 ,  H01L29/7887 ,  H01L29/7923

摘要： A method for operating a P-channel SONOS memory device that has a charge trapping layer located on a substrate, a gate electrode located on the trapping layer, two doped regions located in the substrate at each side of the charge trapping layer. The two doped regions are set to be a drain region and a source region. When a programming action is intended, the gate electrode and the drain region are applied with a first negative high-level bias, and the source region and the substrate are applied with a grounded voltage. When an erasing action is intended, the gate electrode is a second negative bias which is smaller than the first negative voltage in absolute value. In the mean time, the drain region is applied with the third negative bias and the substrate is applied with a grounded voltage. The third negative voltage is larger than the second negative bias in absolute value.

摘要翻译： 一种用于操作具有位于衬底上的电荷俘获层的P沟道SONOS存储器件的方法，位于俘获层上的栅电极，位于电荷俘获层每侧的衬底中的两个掺杂区。 两个掺杂区域被设置为漏极区域和源极区域。 当需要编程动作时，栅极电极和漏极区域被施加第一负的高电平偏置，并且源区域和衬底被施加接地电压。 当需要擦除动作时，栅电极是比绝对值中的第一负电压小的第二负偏压。 同时，漏极区域被施加第三负偏压，并且衬底被施加接地电压。 第三负电压大于绝对值中的第二负偏压。

公开(公告)号：US20080158966A1

公开(公告)日：2008-07-03

申请号：US11617007

申请日：2006-12-28

申请人： Ming-Shiang Chen ,  Wen-Pin Lu ,  I-Jen Huang ,  Chi Yuan Chin ,  Nian-Kai Zous

发明人： Ming-Shiang Chen ,  Wen-Pin Lu ,  I-Jen Huang ,  Chi Yuan Chin ,  Nian-Kai Zous

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/10 ,  G11C16/3454 ,  G11C16/3459

摘要： Methods for programming and program verification of a flash memory are described that ease the buried drain contact induced operation and increase the retention window. In a first aspect of the invention, a program operation method provides varying program biases which are applied to different groups of memory cells. The program biases can be supplied as drain bias voltages or gate bias voltages. The program biases vary depending on which group of memory cells is programmed. In one embodiment, a first drain voltage VD1 is applied to the first group of memory cells M0 and Mn. A second drain voltage VD2 is applied to the second group of memory cells M1 and Mn-1, where VD2=VD1+ΔVD. In a second aspect of the invention, a plurality of program verification voltage levels are selected to verify that the memory cells pass the program voltage levels.

摘要翻译： 描述了用于快速存储器的编程和程序验证的方法，其易于埋入漏极接触引起的操作并增加保持窗口。 在本发明的第一方面，一种程序操作方法提供了应用于不同组的存储单元的变化的程序偏移。 程序偏置可以作为漏极偏置电压或栅极偏置电压提供。 程序偏移根据编程的哪组存储单元而有所不同。 在一个实施例中，第一漏极电压V SUB D1被施加到第一组存储器单元M 0和M N n。 第二漏极电压V SUB D2被施加到第二组存储器单元M 1和M N-1 N，其中V D2 = V D1 + +ΔVD D 在本发明的第二方面中，选择多个程序验证电压电平以验证存储单元是否通过编程电压电平。

公开(公告)号：US06812099B2

公开(公告)日：2004-11-02

申请号：US10139119

申请日：2002-05-02

申请人： Hung-Sui Lin ,  Nian-Kai Zous ,  Tao-Cheng Lu ,  Kent Kuohua Chang

发明人： Hung-Sui Lin ,  Nian-Kai Zous ,  Tao-Cheng Lu ,  Kent Kuohua Chang

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324

摘要： A method for fabricating a non-volatile memory having a P-type floating gate is described. A tunneling layer is formed on a substrate and then a first patterned polysilicon layer is formed on the tunneling layer. A buried drain is formed in the substrate beside the first polysilicon layer and then an insulating structure is formed on the tunneling layer on the buried drain. Thereafter, a second polysilicon layer is formed on the first polysilicon layer to constitute a floating gate together with the first polysilicon layer. A P-type ion is implanted into the second polysilicon layer and then a dielectric layer and a control gate are sequentially formed on the floating gate. A thermal process is then performed to make the P-type, ion in the second polysilicon layer diffuse into the first polysilicon layer.

摘要翻译： 描述了一种用于制造具有P型浮动栅极的非易失性存储器的方法。 在衬底上形成隧道层，然后在隧道层上形成第一图案化多晶硅层。 在第一多晶硅层旁边的衬底中形成掩埋漏极，然后在埋漏极上的隧穿层上形成绝缘结构。 此后，在第一多晶硅层上形成第二多晶硅层，以与第一多晶硅层一起构成浮置栅极。 将P型离子注入到第二多晶硅层中，然后在浮栅上依次形成电介质层和控制栅。 然后进行热处理以使第二多晶硅层中的P型离子扩散到第一多晶硅层中。

公开(公告)号：US20100085809A1

公开(公告)日：2010-04-08

申请号：US12636095

申请日：2009-12-11

申请人： Yung-Feng LIN ,  Nian-Kai Zous ,  I-Jen Huang ,  Yin-Jen Chen

发明人： Yung-Feng LIN ,  Nian-Kai Zous ,  I-Jen Huang ,  Yin-Jen Chen

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C11/5642 ,  G11C2211/5634

摘要： A multi-bit flash memory and a reading method thereof. Multiple reference memory cells for saving reserved data are provided to operate together with multiple data memory cells. Before the data memory cells are read, data stored in the reference memory cell is sensed based on a present reference current. Then, a value of a new reference current for reading the data memory cells is determined according to a difference between the sensed data and the reserved data.

摘要翻译： 一种多位闪存及其读取方法。 提供用于保存预留数据的多个参考存储器单元以与多个数据存储单元一起操作。 在读取数据存储单元之前，基于当前的参考电流感测存储在参考存储器单元中的数据。 然后，根据感测数据和保留数据之间的差异来确定读取数据存储单元的新参考电流的值。