公开(公告)号：US06812099B2

公开(公告)日：2004-11-02

申请号：US10139119

申请日：2002-05-02

申请人： Hung-Sui Lin ,  Nian-Kai Zous ,  Tao-Cheng Lu ,  Kent Kuohua Chang

发明人： Hung-Sui Lin ,  Nian-Kai Zous ,  Tao-Cheng Lu ,  Kent Kuohua Chang

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324

摘要： A method for fabricating a non-volatile memory having a P-type floating gate is described. A tunneling layer is formed on a substrate and then a first patterned polysilicon layer is formed on the tunneling layer. A buried drain is formed in the substrate beside the first polysilicon layer and then an insulating structure is formed on the tunneling layer on the buried drain. Thereafter, a second polysilicon layer is formed on the first polysilicon layer to constitute a floating gate together with the first polysilicon layer. A P-type ion is implanted into the second polysilicon layer and then a dielectric layer and a control gate are sequentially formed on the floating gate. A thermal process is then performed to make the P-type, ion in the second polysilicon layer diffuse into the first polysilicon layer.

摘要翻译： 描述了一种用于制造具有P型浮动栅极的非易失性存储器的方法。 在衬底上形成隧道层，然后在隧道层上形成第一图案化多晶硅层。 在第一多晶硅层旁边的衬底中形成掩埋漏极，然后在埋漏极上的隧穿层上形成绝缘结构。 此后，在第一多晶硅层上形成第二多晶硅层，以与第一多晶硅层一起构成浮置栅极。 将P型离子注入到第二多晶硅层中，然后在浮栅上依次形成电介质层和控制栅。 然后进行热处理以使第二多晶硅层中的P型离子扩散到第一多晶硅层中。

公开(公告)号：US06720614B2

公开(公告)日：2004-04-13

申请号：US10005270

申请日：2001-12-04

申请人： Hung-Sui Lin ,  Nian-Kai Zous ,  Han-Chao Lai ,  Tao-Cheng Lu

发明人： Hung-Sui Lin ,  Nian-Kai Zous ,  Han-Chao Lai ,  Tao-Cheng Lu

IPC分类号： H01L29788

CPC分类号： G11C16/0475 ,  H01L29/7887 ,  H01L29/7923

摘要： A method for operating a P-channel SONOS memory device that has a charge trapping layer located on a substrate, a gate electrode located on the trapping layer, two doped regions located in the substrate at each side of the charge trapping layer. The two doped regions are set to be a drain region and a source region. When a programming action is intended, the gate electrode and the drain region are applied with a first negative high-level bias, and the source region and the substrate are applied with a grounded voltage. When an erasing action is intended, the gate electrode is a second negative bias which is smaller than the first negative voltage in absolute value. In the mean time, the drain region is applied with the third negative bias and the substrate is applied with a grounded voltage. The third negative voltage is larger than the second negative bias in absolute value.

摘要翻译： 一种用于操作具有位于衬底上的电荷俘获层的P沟道SONOS存储器件的方法，位于俘获层上的栅电极，位于电荷俘获层每侧的衬底中的两个掺杂区。 两个掺杂区域被设置为漏极区域和源极区域。 当需要编程动作时，栅极电极和漏极区域被施加第一负的高电平偏置，并且源区域和衬底被施加接地电压。 当需要擦除动作时，栅电极是比绝对值中的第一负电压小的第二负偏压。 同时，漏极区域被施加第三负偏压，并且衬底被施加接地电压。 第三负电压大于绝对值中的第二负偏压。

公开(公告)号：US20050237813A1

公开(公告)日：2005-10-27

申请号：US10876255

申请日：2004-06-24

申请人： Nian-Kai Zous ,  Wen-Jer Tsai ,  Hung-Yueh Chen ,  Tao-Cheng Lu

发明人： Nian-Kai Zous ,  Wen-Jer Tsai ,  Hung-Yueh Chen ,  Tao-Cheng Lu

IPC分类号： G11C16/04 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/0466 ,  H01L29/7885 ,  H01L29/792

摘要： A process and a memory architecture for operating a charge trapping memory cell is provided. The method for operating the memory cell includes establishing a high threshold state in the memory cell by injecting negative charge into the charge trapping structure to set a high state threshold. The method includes using a self-converging biasing procedure to establish a low threshold state for the memory cell by reducing the negative charge in the charge trapping structure to set the threshold voltage for the cell to a low threshold state. The negative charge is reduced in the memory cell by applying a bias procedure including at least one bias pulse. The bias pulse balances charge flow into and out of the charge trapping layer to achieve self-convergence on a desired threshold level. Thereby, an over-erase condition is avoided.

摘要翻译： 提供了用于操作电荷捕获存储器单元的过程和存储器架构。 用于操作存储单元的方法包括通过将负电荷注入到电荷俘获结构中来建立高的阈值状态，以设置高状态阈值。 该方法包括使用自会聚偏移过程来通过减少电荷俘获结构中的负电荷来为存储器单元建立低阈值状态，以将电池的阈值电压设置为低阈值状态。 通过施加包括至少一个偏置脉冲的偏置过程，在存储单元中负电荷减小。 偏置脉冲平衡进入和离开电荷捕获层的电荷流，以在期望的阈值水平上实现自会聚。 从而避免了过度擦除的情况。

公开(公告)号：US06524913B1

公开(公告)日：2003-02-25

申请号：US10004934

申请日：2001-12-04

申请人： Hung-Sui Lin ,  Han-Chao Lai ,  Tao-Cheng Lu

发明人： Hung-Sui Lin ,  Han-Chao Lai ,  Tao-Cheng Lu

IPC分类号： H01L218247

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/792

摘要： A method of fabricating a non-volatile memory, in which a charge-trapping layer consisting of insulating materials and bar-like conductive layers to be patterned into the gates are formed at first. The buried bit-lines are formed in the substrate between the bar-like conductive layers. Each of the buried bit-lines extends into the substrate under a portion of an adjacent high-K spacer, but not to the substrate under an adjacent bar-like conductive layer. High-K spacers are formed on the side-walls of the bar-like conductive layers. Then the bar-like conductive layers are patterned into the gates, and word-lines are formed on the substrate to electrically connect with the gates. The material of the high-K spacer has a dielectric constant and the high-K spacer has a width, such that a channel will extend to the substrate under the high-K spacer and connect with the buried bit-line when the non-volatile memory is operated.

摘要翻译： 一种制造非易失性存储器的方法，其中首先形成由绝缘材料构成的电荷捕获层和待形成栅格的棒状导电层。 在棒状导电层之间的衬底中形成掩埋位线。 每个埋置的位线在相邻的高K间隔物的一部分下延伸到衬底中，但不延伸到相邻的棒状导电层下方的衬底。 在棒状导电层的侧壁上形成高K隔离物。 然后将棒状导电层图案化成栅极，并且在基板上形成字线以与栅极电连接。 高K间隔物的材料具有介电常数，高K间隔物具有宽度，使得沟道将在高K间隔物下延伸到衬底，并且当非挥发性的时候与掩埋位线连接 内存被操作

公开(公告)号：US06455388B1

公开(公告)日：2002-09-24

申请号：US10099802

申请日：2002-03-13

申请人： Han-Chao Lai ,  Hung-Sui Lin ,  Tao-Cheng Lu

发明人： Han-Chao Lai ,  Hung-Sui Lin ,  Tao-Cheng Lu

IPC分类号： H01L21336

CPC分类号： H01L29/66492 ,  H01L21/2652 ,  H01L21/26586 ,  H01L29/665

摘要： A method of fabricating a MOS transistor. First, a substrate having a gate electrode and spacers on the gate electrode sidewalls is provided. A source/drain region is formed in the substrate outside the outer edge of the spacer sidewalls. A self-aligned silicide layer is formed over the exposed surface of the gate electrode and the source/drain regions. A portion of the spacers is removed by etching to form a sharp-angled triangular spacer on the sidewalls of the gate electrode. A pocket implantation of the substrate is carried out to form a pocket region inside the substrate under the side edges of the gate electrode. By controlling the setting of the energy level and the implant angle in the pocket implantation, a precise distribution of the dopants at desired locations within the substrate is reproduced. Finally, the sharp-angled spacers are removed and then a light implantation is conducted to form source/drain extension regions in the substrate on each side of the gate electrode.

摘要翻译： 一种制造MOS晶体管的方法。 首先，提供在栅电极侧壁上具有栅电极和间隔物的基板。 源极/漏极区域形成在衬垫外侧边缘外侧的衬底中。 在栅极电极和源极/漏极区域的暴露表面上形成自对准的硅化物层。 通过蚀刻去除一部分间隔物，以在栅电极的侧壁上形成锐角三角形间隔物。 进行基板的袋式注入，以在栅电极的侧边缘下方的基板内部形成袋区域。 通过控制袋注入中的能级和植入角度的设定，再现了衬底内所需位置处的掺杂剂的精确分布。 最后，去除尖锐的间隔物，然后进行光注入以在栅电极的每一侧上的衬底中形成源极/漏极延伸区域。

公开(公告)号：US06482709B1

公开(公告)日：2002-11-19

申请号：US09900578

申请日：2001-07-06

申请人： Han-Chao Lai ,  Hung-Sui Lin ,  Tao-Cheng Lu

发明人： Han-Chao Lai ,  Hung-Sui Lin ,  Tao-Cheng Lu

IPC分类号： H01L21336

CPC分类号： H01L21/28035 ,  H01L21/26506 ,  H01L29/4916

摘要： A manufacturing method of a MOS transistor. A gate oxide layer and a polysilicon layer are successively formed on a substrate. A nitrogen ion implantation is performed to implant nitrogen ions into the contact region of the polysilicon layer with the gate dielectric layer. An annealing is performed in order to enlarge the polysilicon grains within the polysilicon layer. The polysilicon layer is patterned to form a gate. A dopant is implanted into the substrate on the sides of the gate, thereby forming a source/drain region.

摘要翻译： 一种MOS晶体管的制造方法。 栅极氧化层和多晶硅层依次形成在基板上。 进行氮离子注入以将氮离子注入到具有栅极介电层的多晶硅层的接触区域中。 为了扩大多晶硅层内的多晶硅晶粒，进行退火。 图案化多晶硅层以形成栅极。 掺杂剂注入栅极侧面的衬底中，由此形成源/漏区。

公开(公告)号：US06671209B2

公开(公告)日：2003-12-30

申请号：US10035514

申请日：2001-10-22

申请人： Hung-Sui Lin ,  Han-Chao Lai ,  Tao-Cheng Lu

发明人： Hung-Sui Lin ,  Han-Chao Lai ,  Tao-Cheng Lu

IPC分类号： G11C1604

CPC分类号： G11C16/14

摘要： An erasing method for a p-channel nitride read only memory. The method is used for a p-channel nitride read only memory having charges stored in a charge-trapping layer. A positive voltage is applied to the control gate and a negative voltage to the drain; also, the source is floating and the n-well is grounded. The voltage difference between the positive voltage applied to the control gate and the negative voltage to the drain is sufficient to trigger a band-to-band induced hot electron injection to erase the p-channel nitride read only memory.

摘要翻译： 用于p沟道氮化物只读存储器的擦除方法。 该方法用于具有存储在电荷捕获层中的电荷的p沟道氮化物只读存储器。 向控制栅极施加正电压，向漏极施加负电压; 源也是浮动的，n阱是接地的。 施加到控制栅极的正电压和到漏极的负电压之间的电压差足以触发带间感应的热电子注入以擦除p沟道氮化物只读存储器。

公开(公告)号：US06492235B2

公开(公告)日：2002-12-10

申请号：US09770550

申请日：2001-01-26

申请人： Han-Chao Lai ,  Tao-Cheng Lu ,  Hung-Sui Lin

发明人： Han-Chao Lai ,  Tao-Cheng Lu ,  Hung-Sui Lin

IPC分类号： H01L21336

CPC分类号： H01L29/66492 ,  H01L29/665 ,  H01L29/6653

摘要： A method for forming extension by using double etch spacer. The method includes at least the following steps. First a semiconductor substrate is provided. Then, the gate is formed on the substrate. A first spacer is formed on a sidewall of the gate. Then, numerous first ions are implanted in the substrate by a mask of both the gate and the first spacer to form the source/drain region. Then, the second spacer is formed by etching the first spacer, wherein the width of the second spacer is less than the width of the first spacer. Finally, numerous second ions are implanted in the substrate by a mask of both the gate and the second spacer to form an extension.

摘要翻译： 通过使用双蚀刻间隔物形成延伸的方法。 该方法至少包括以下步骤。 首先提供半导体衬底。 然后，在基板上形成栅极。 第一间隔件形成在栅极的侧壁上。 然后，通过栅极和第一间隔物的掩模将许多第一离子注入到衬底中以形成源极/漏极区。 然后，通过蚀刻第一间隔物形成第二间隔物，其中第二间隔物的宽度小于第一间隔物的宽度。 最后，通过栅极和第二间隔物的掩模将许多第二离子注入到衬底中以形成延伸。

公开(公告)号：US06458643B1

公开(公告)日：2002-10-01

申请号：US09681984

申请日：2001-07-03

申请人： Han-Chao Lai ,  Tao-Cheng Lu ,  Hung-Sui Lin

发明人： Han-Chao Lai ,  Tao-Cheng Lu ,  Hung-Sui Lin

IPC分类号： H01L218238

CPC分类号： H01L29/7833 ,  H01L21/2652 ,  H01L21/324 ,  H01L29/66492 ,  H01L29/6659

摘要： A semiconductor substrate is provided with at least a gate formed on the semiconductor substrate. A first ion implantation process is performed to form a pocket implant region within the semiconductor substrate beneath the gate. Following the first ion implantation process, a first rapid thermal annealing (RTA) process is immediately performed to reduce TED effects resulting from the first ion implantation process. Thereafter, a second implantation process is performed to form a source extension doping region and a drain extension doping region within the semiconductor substrate adjacent to the gate. A source doping region and a drain doping region are then formed within the semiconductor substrate adjacent to the gate. Finally, a second RTA process is performed to simultaneously activate dopants in the source extension doping region, the drain extension doping region, the source doping region and the drain doping region.

摘要翻译： 半导体衬底至少设置有形成在半导体衬底上的栅极。 执行第一离子注入工艺以在栅极下方的半导体衬底内形成凹穴注入区域。 在第一离子注入工艺之后，立即执行第一快速热退火（RTA）工艺以降低由第一离子注入工艺产生的TED效应。 此后，执行第二注入工艺以在与栅极相邻的半导体衬底内形成源极延伸掺杂区域和漏极延伸掺杂区域。 然后在与栅极相邻的半导体衬底内形成源极掺杂区域和漏极掺杂区域。 最后，执行第二RTA工艺以同时激活源延伸掺杂区域，漏极延伸掺杂区域，源极掺杂区域和漏极掺杂区域中的掺杂剂。

公开(公告)号：US06620693B2

公开(公告)日：2003-09-16

申请号：US10055491

申请日：2002-01-22

申请人： Han-Chao Lai ,  Hung-Sui Lin ,  Tao-Cheng Lu

发明人： Han-Chao Lai ,  Hung-Sui Lin ,  Tao-Cheng Lu

IPC分类号： H01L218234

CPC分类号： H01L27/11213 ,  H01L27/105 ,  H01L27/1126 ,  H01L27/11293

摘要： A method for fabricating a non-volatile memory is described. A planar doped region is formed in the substrate at first. A mask layer and a patterned photoresist layer are sequentially formed on the substrate. A plurality of trenches is formed in the substrate with the patterned photoresist layer as a mask to divide the planar doped region into a plurality of bit-lines. The patterned photoresist layer is removed and then a recovering process is performed to recover the side-walls and the bottoms of the trenches from the damages caused by the trench etching step; The mask layer is removed. A dielectric layer is formed on the substrate and then a plurality of word-lines is formed on the dielectric layer.

摘要翻译： 描述了制造非易失性存储器的方法。 首先在衬底中形成平面掺杂区域。 在衬底上依次形成掩模层和图案化的光致抗蚀剂层。 在衬底中形成多个沟槽，其中图案化的光致抗蚀剂层作为掩模将平面掺杂区域分成多个位线。 去除图案化的光致抗蚀剂层，然后执行恢复过程以从沟槽蚀刻步骤引起的损伤中回收沟槽的侧壁和底部; 去除掩模层。 在基板上形成电介质层，然后在电介质层上形成多个字线。