公开(公告)号：US4630356A

公开(公告)日：1986-12-23

申请号：US777800

申请日：1985-09-19

申请人： Rosemary Christie ,  Bao-Tai Hwang ,  San-Mei Ku ,  Janet M. Sickler

发明人： Rosemary Christie ,  Bao-Tai Hwang ,  San-Mei Ku ,  Janet M. Sickler

IPC分类号： H01L21/76 ,  H01L21/306 ,  H01L21/308 ,  H01L21/316 ,  H01L21/762 ,  H01L21/467 ,  H01L21/94

CPC分类号： H01L21/7621 ,  H01L21/3081

摘要： Disclosed is a method of forming in a monocrystalline silicon body an optimum recessed oxide isolation structure with reduced steepness of the bird's neck. Starting from a monocrystalline silicon body, there is formed thereon a layered structure of first silicon dioxide, polycrystalline silicon, second silicon dioxide and silicon nitride, in that order. The layers are patterned to form openings in the structure at the areas where it is desired to form the oxide isolation pattern within the silicon body. The exposed areas of the silicon body are anisotropically reactive ion etched to an initial portion of the desired depth obtaining the corresponding portion of the trench having substantially vertical walls. Then by chemical etching the trench is extended to a final portion of the desired depth obtaining inwardly sloped walls in the final portion. The body is then thermally oxidized until the desired oxide isolation penetrates to the desired depth within the silicon body.

摘要翻译： 公开了一种在单晶硅体中形成具有降低的脖子陡度的最佳凹陷氧化物隔离结构的方法。 从单晶硅体开始，依次形成第一二氧化硅，多晶硅，第二二氧化硅和氮化硅的分层结构。 这些层被图案化以在期望在硅体内形成氧化物隔离图案的区域的结构中形成开口。 硅体的暴露区域是各向异性反应离子蚀刻到期望深度的初始部分，获得具有基本垂直壁的沟槽的相应部分。 然后通过化学蚀刻将沟槽延伸到所需深度的最后部分，从而获得最终部分中的向内倾斜的壁。 然后将身体热氧化直到所需的氧化物隔离渗入硅体内所需的深度。

公开(公告)号：US4871684A

公开(公告)日：1989-10-03

申请号：US114190

申请日：1987-10-29

申请人： Reinhard Glang ,  San-Mei Ku

发明人： Reinhard Glang ,  San-Mei Ku

IPC分类号： H01L29/73 ,  H01L21/033 ,  H01L21/285 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8228 ,  H01L27/082 ,  H01L29/08 ,  H01L29/732

CPC分类号： H01L29/66272 ,  H01L21/033 ,  H01L21/28525 ,  H01L21/8222 ,  H01L29/0804

摘要： A semiconductor process for fabricating bipolar devices of one type and extendible to include bipolar devices of a second type in the same epi-layer. The process protects selected surfaces of the epi-layer against deleterious processes associated with the formation of future emitter/contact regions for the devices. Subsequently, such emitter/contact regions are formed beneath such protected surfaces and contribute to enhanced device performance. The process also provides improved planarization of an insulating layer on the epi-layer by chemical-mechanical polishing. The planarization in conjunction with a mask formed in the insulating layer facilitates the formation of self-aligned emitter/base regions to appropriate thicknesses for high performance devices.

公开(公告)号：US5015594A

公开(公告)日：1991-05-14

申请号：US261952

申请日：1988-10-24

申请人： Shao-Fu S. Chu ,  San-Mei Ku ,  Russell C. Lange ,  Joseph F. Shephard ,  Paul J. Tsang ,  Wen-Yuan Wang

发明人： Shao-Fu S. Chu ,  San-Mei Ku ,  Russell C. Lange ,  Joseph F. Shephard ,  Paul J. Tsang ,  Wen-Yuan Wang

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/60 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732

CPC分类号： H01L21/76897 ,  H01L21/8249 ,  Y10S148/009

摘要： A method of forming a semiconductor device on a body of semiconductor material having a first doped region of a first conductivity type, comprising the steps of: forming a stud over the first doped region; using the stud as a mask to form a second doped region of a second conductivity type in the surface of the first doped region adjoining the stud; forming a sidewall of insulating material on the stud; forming a first device contact within the sidewall; and forming a second device contact over the second doped region adjoining the sidewall, such that the first and second electrical contacts are separated by the sidewall.In accordance with an embodiment of the present invention, the step of forming the second device contact includes the steps of forming a layer of conductive material generally conformally over the first doped region and the stud, and then planarizing the layer of conductive material to a height equal to or less than that of the sidewalls. The second contact is thus self-aligned with the first and second doped regions and the first device contact.The method of the present invention can be utilized to fabricate bipolar transistors, insulated gate transistors, and BICMOS logic including both types of transistors. It can further be used to fabricate any other type of semiconductor device which utilizes the self-aligned, closely spaced device regions and contacts of the present invention.

公开(公告)号：US3982967A

公开(公告)日：1976-09-28

申请号：US562370

申请日：1975-03-26

申请人： San-Mei Ku ,  Charles A. Pillus ,  Michael R. Poponiak ,  Robert O. Schwenker

发明人： San-Mei Ku ,  Charles A. Pillus ,  Michael R. Poponiak ,  Robert O. Schwenker

IPC分类号： C30B31/22 ,  H01L21/22 ,  H01L21/265 ,  H01L21/761 ,  H01L21/263

CPC分类号： H01L21/263 ,  H01L21/26506

摘要： In integrated circuit fabrication, a method is provided for simultaneously forming two regions of the same conductivity-type such as the base and isolation regions. In one embodiment, an epitaxial layer of one conductivity-type is formed on a substrate of opposite conductivity-type, after which dopant ions of the opposite conductivity-type are introduced into the epitaxial surface areas which are to provide the base and isolation regions, and in addition, the isolation regions are bombarded with non-dopant ions having a maximum atomic number of two, e.g., hydrogen or helium ion while the base regions are appropriately masked and remain umbombarded, said bombardment is carried out at temperatures below 300.degree. C, preferably room temperature. The bombardment is preferably carried out so that the non-dopant ions are implanted primarily in regions below the isolation regions. Next, the wafer is heated at a temperature at a range of from 600.degree. - 900.degree. C which is substantially below normal drive-in diffusion temperatures for unbombarded doped regions. The heating to be maintained for a period sufficient to drive-in diffuse the bombarded isolation regions through the epitaxial layer into contact with the substrate but is insufficient to drive-in the unbombarded base regions to such a depth.

摘要翻译： 在集成电路制造中，提供了一种用于同时形成相同导电类型的两个区域的方法，例如基极和隔离区域。 在一个实施例中，在相反导电型的衬底上形成一种导电类型的外延层，之后将相反导电类型的掺杂剂离子引入到要提供基极和隔离区域的外延表面区域中， 此外，隔离区域用最大原子数为2的非掺杂离子（例如氢或氦离子）进行轰击，同时基底区域被适当地掩蔽并且保持不变，所述轰击在低于300℃的温度下进行 ，优选室温。 优选进行轰击，使得非掺杂剂离子主要被注入在隔离区域下方的区域中。 接下来，将晶片在600-900℃的温度范围内加热，这对于未掺杂的掺杂区域基本上低于正常的驱动扩散温度。 保持加热持续足以驱动的时间段将被轰击的隔离区域通过外延层与基板接触，但是不足以将未轰炸的基极区域驱动到这样的深度。

公开(公告)号：US4467519A

公开(公告)日：1984-08-28

申请号：US384371

申请日：1982-04-01

申请人： Reinhard Glang ,  San-Mei Ku ,  Alfred Schmitt

发明人： Reinhard Glang ,  San-Mei Ku ,  Alfred Schmitt

IPC分类号： H01L29/73 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3215 ,  H01L21/331 ,  H01L21/822 ,  H01L21/8222 ,  H01L27/01 ,  H01L27/04 ,  H01L21/263 ,  H01L21/26 ,  H01L21/425

CPC分类号： H01L28/20 ,  H01L21/32155 ,  H01L21/8222

摘要： A method for fabricating polycrystalline silicon resistors is described which includes deposition of a polycrystalline silicon layer of very fine grain size upon an insulator surface, followed by ion implantation of boron equal to or slightly in excess of the solubility limit of the polycrystalline silicon. This ion implantation is normally done using a screen silicon dioxide surface layer. The structure may be annealed at temperatures of between about 800.degree. C. to 1100.degree. C. for 15 to 180 minutes to control the grain size of the polycrystalline silicon layer, homogenize the distribution of the boron ions throughout the entire film thickness and to raise the concentration of the boron in the silicon grains to the solid solubility limit. The suitable electrical contacts are now made to the polycrystalline silicon layer to form the resistor.

摘要翻译： 描述了一种用于制造多晶硅电阻器的方法，其包括在绝缘体表面上沉积非常细晶粒尺寸的多晶硅层，然后将硼等离子注入等于或稍微超过多晶硅的溶解度极限。 这种离子注入通常使用屏幕二氧化硅表面层进行。 该结构可以在约800℃至1100℃的温度下退火15至180分钟以控制多晶硅层的晶粒尺寸，使硼离子在整个膜厚度上的分布均匀化并提高 硅颗粒中硼的浓度达到固溶度极限。 现在，将合适的电接触件制成多晶硅层以形成电阻器。

公开(公告)号：US4028149A

公开(公告)日：1977-06-07

申请号：US701452

申请日：1976-06-30

申请人： John L. Deines ,  San-Mei Ku ,  Michael R. Poponiak ,  Paul J. Tsang

发明人： John L. Deines ,  San-Mei Ku ,  Michael R. Poponiak ,  Paul J. Tsang

IPC分类号： C30B25/02 ,  C30B29/36 ,  H01L21/04 ,  H01L21/205 ,  H01L21/762 ,  H01L29/267 ,  H01L21/76 ,  H01L21/20 ,  H01L27/04

CPC分类号： H01L29/66068 ,  H01L21/76202 ,  H01L29/267 ,  Y10S148/051 ,  Y10S148/117 ,  Y10S148/148 ,  Y10S438/96

摘要： A method for forming monocrystalline silicon carbide on a silicon substrate by converting a portion of the monocrystalline silicon substrate into a porous silicon substance by anodic treatment carried out in an aqueous solution of hydrofluoric acid, heating the resultant substrate to a temperature in the range of 1050.degree. C to 1250.degree. C in an atmosphere that includes a hydrocarbon gas for a time sufficient to react the porous silicon and the gas, thereby forming a layer of monocrystalline silicon carbide on the silicon substrate.

摘要翻译： 通过在氢氟酸水溶液中进行阳极处理，将单晶硅衬底的一部分转化为多孔硅物质，在硅衬底上形成单晶碳化硅的方法，将所得衬底加热至1050℃ 在包含烃气体的气氛中，在足以使多孔硅和气体反应的时间内，从而在硅衬底上形成一层单晶碳化硅。

公开(公告)号：US3946417A

公开(公告)日：1976-03-23

申请号：US496481

申请日：1974-08-12

申请人： William N. Jacobus, Jr. ,  San-Mei Ku

发明人： William N. Jacobus, Jr. ,  San-Mei Ku

IPC分类号： H01L27/15 ,  H01L33/44 ,  H01L33/00 ,  H01L29/34

CPC分类号： H01L33/44 ,  H01L27/153

摘要： Disclosed is a semiconductor light emitting diode (LED) array in which "cross-talk" between adjacent diodes in the array is minimized. The disclosed LED arrays have an absorbing layer on the backside of the devices and/or a guard ring region surrounding each device in order to absorb spurious reflections within the semiconductor crystal. Disclosed also is a method of making improved light emitting diodes (LED's).

摘要翻译： 公开了半导体发光二极管（LED）阵列，其中阵列中相邻二极管之间的“串扰”最小化。 所公开的LED阵列在器件的背面具有吸收层和/或围绕每个器件的保护环区域，以便吸收半导体晶体内的假反射。 还公开了制造改进的发光二极管（LED）的方法。

公开(公告)号：US5227658A

公开(公告)日：1993-07-13

申请号：US781429

申请日：1991-10-23

申请人： Klaus D. Beyer ,  San-Mei Ku ,  Victor J. Silvestri ,  Andrie S. Yapsir

发明人： Klaus D. Beyer ,  San-Mei Ku ,  Victor J. Silvestri ,  Andrie S. Yapsir

IPC分类号： H01L21/76 ,  H01L21/764 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L21/764

摘要： A method for isolating areas of silicon from a substrate 50 includes the steps of: providing a buried N+ region 52 in the substrate; forming an intrinsic epitaxial layer 12 onto the N+ region; etching trenches 18, 20 through the intrinsic epitaxial layer to thereby form a desired isolation region 16 of intrinsic epitaxial material; laterally etching a cavity 22 underneath the desired isolation region; and, forming an insulation layer 24 of insulation material along the bottom of the desired isolation region exposed by the former etching steps.

公开(公告)号：US5010039A

公开(公告)日：1991-04-23

申请号：US351993

申请日：1989-05-15

申请人： San-Mei Ku ,  Kathleen A. Perry

发明人： San-Mei Ku ,  Kathleen A. Perry

IPC分类号： H01L29/73 ,  H01L21/285 ,  H01L21/302 ,  H01L21/331 ,  H01L21/768 ,  H01L29/732

CPC分类号： H01L21/76802 ,  H01L21/28525 ,  Y10S148/011 ,  Y10S148/124 ,  Y10S438/97

摘要： A method of forming semiconductor device contacts includes the steps of: providing a semiconductor substrate having at least two features thereon whereat it is desired to make electrical connections; forming a layer of etch stop material having a first etch characteristic over each of the features; forming a layer of dielectric material having a second etch characteristic over each of the features; simultaneously etching at least two vias through the layer of dielectric material using an etchant selective to the layer of dielectric material so as to substantially stop on the layer of etch stop material, the at least two vias including a via over each of the features; and extending the vias through the layer of etch stop material so as to expose the features for subsequent electrical connections.