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1.发明授权Method for fabricating a MOSFET with raised STI isolation self-aligned to the gate stack 失效用于制造具有与门堆叠自对准的凸起STI隔离的MOSFET的方法
公开(公告)号：US6022781A
公开(公告)日：2000-02-08
申请号：US772708
申请日：1996-12-23
IPC分类号： H01L21/8242 , H01L21/08 , H01L29/00 , H01L29/76
CPC分类号： H01L27/10861
摘要： A semiconductor structure comprising a transistor having a gate conductor that has first and second edges bounded by raised isolation structures (e.g. STI). A source diffusion is self-aligned to the third edge and a drain diffusion is self-aligned to the fourth edge of the gate electrode.
摘要翻译： 一种半导体结构，包括具有栅极导体的晶体管，栅极导体具有由凸起的隔离结构（例如STI）限定的第一和第二边缘。 源极扩散与第三边缘自对准，漏极扩散与栅电极的第四边缘自对准。
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2.发明授权
公开(公告)号：US5539229A
公开(公告)日：1996-07-23
申请号：US365729
申请日：1994-12-28
IPC分类号： H01L21/8242 , H01L27/08 , H01L29/00 , H01L29/76
CPC分类号： H01L27/10861
摘要： A semiconductor structure comprising a transistor having a gate conductor that has first and second edges bounded by raised isolation structures (e.g. STI). A source diffusion is self-aligned to the third edge and a drain diffusion is self-aligned to the fourth edge of the gate electrode.
摘要翻译： 一种半导体结构，包括具有栅极导体的晶体管，栅极导体具有由凸起的隔离结构（例如STI）限定的第一和第二边缘。 源极扩散与第三边缘自对准，漏极扩散与栅电极的第四边缘自对准。
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公开(公告)号：US4725562A
公开(公告)日：1988-02-16
申请号：US844655
申请日：1986-03-27
IPC分类号： H01L21/76 , H01L21/74 , H01L21/762 , H01L21/8224 , H01L21/8228 , H01L27/082 , H01L21/302
CPC分类号： H01L21/76237 , H01L21/743
摘要： A method or process is provided for making a semiconductor structure which includes the steps of forming in a semiconductor body a P/N junction and an opening in an insulating layer disposed on the surface of the semiconductor body. A trench is then formed in the semiconductor layer having a sidewall located along a given plane through the opening and through the P/N junction. An insulating material is disposed within the trench and over the insulating layer and a block or segment of material is located over the trench so as to extend a given distance from the trench over the upper surface of the body. The insulating material and the block are then etched so as to remove the block and the insulating material located along the sides of the block. A layer of low viscosity material is formed over the semiconductor body so as to cover the remaining portion of the insulating material, the layer of low viscosity material and the insulating material having similar etch rates. The layer of low viscosity material and the insulating material are then simultaneously etched directionally until all of the layer of low viscosity material is removed. Metallic contacts may now be formed on the surface of the semiconductor body without the concern that the metallic material will seep or enter into the trench causing a short at the P/N junction.
摘要翻译： 提供了一种用于制造半导体结构的方法或工艺，该半导体结构包括以下步骤：在半导体本体中形成P / N结和设置在半导体本体表面上的绝缘层中的开口。 然后在半导体层中形成沟槽，该沟槽具有沿着给定平面穿过开口并通过P / N结的侧壁。 绝缘材料设置在沟槽内并在绝缘层之上，并且材料块或段被定位在沟槽上方，以便在主体的上表面上从沟槽延伸给定的距离。 然后蚀刻绝缘材料和块，以便去除沿着块的侧面定位的块和绝缘材料。 在半导体主体上形成一层低粘度材料，以覆盖绝缘材料的剩余部分，低粘度材料层和具有相似蚀刻速率的绝缘材料。 然后同时对低粘度材料层和绝缘材料层进行定向蚀刻，直到所有的低粘度材料层被去除。 现在可以在半导体本体的表面上形成金属接触，而不用担心金属材料将渗入或进入沟槽，导致P / N结处的短路。
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4.发明授权Semiconductor-on-insulator apparatus, device and system with buried decoupling capacitors 有权绝缘体上半导体器件，具有埋入去耦电容器的器件和系统公开(公告)号：US08618633B2
公开(公告)日：2013-12-31
申请号：US13357322
申请日：2012-01-24
申请人： Badih El-Kareh
发明人： Badih El-Kareh
IPC分类号： H01L21/02
CPC分类号： H01L27/1203 , H01L21/84 , H01L23/5223 , H01L29/94 , H01L2924/0002 , H01L2924/00
摘要： A buried decoupling capacitor apparatus and method are provided. According to various embodiments, a buried decoupling capacitor apparatus includes a semiconductor-on-insulator substrate having a buried insulator region and top semiconductor region on the buried insulator region. The apparatus embodiment also includes a first capacitor plate having a doped region in the top semiconductor region in the semiconductor-on-insulator substrate. The apparatus embodiment further includes a dielectric material on the first capacitor plate, and a second capacitor plate on the dielectric material. According to various embodiments, the first capacitor plate, the dielectric material and the second capacitor plate form a decoupling capacitor for use in an integrated circuit.
摘要翻译： 提供了一种埋地去耦电容器装置和方法。 根据各种实施例，掩埋去耦电容器装置包括在绝缘体区域上具有掩埋绝缘体区域和顶部半导体区域的绝缘体上半导体衬底。 该装置实施例还包括在绝缘体上半导体衬底中的顶部半导体区域中具有掺杂区域的第一电容器板。 该装置实施例还包括在第一电容器板上的电介质材料和介电材料上的第二电容器板。 根据各种实施例，第一电容器板，电介质材料和第二电容器板形成用于集成电路的去耦电容器。
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公开(公告)号：US07615425B2
公开(公告)日：2009-11-10
申请号：US11504412
申请日：2006-08-15
IPC分类号： H01L21/337
CPC分类号： H01L29/808 , H01L29/0607 , H01L29/66901
摘要： The disclosure herein pertains to fashioning an n channel junction field effect transistor (NJFET) and/or a p channel junction field effect transistor (PJFET) with an open drain, where the open drain allows the transistors to operate at higher voltages before experiencing gate leakage current. The open drain allows the voltage to be increased several fold without increasing the size of the transistors. Opening the drain essentially spreads equipotential lines of respective electric fields developed at the drains of the devices so that the local electric fields, and hence the impact ionization rates are reduced to redirect current below the surface of the transistors.
摘要翻译： 本文的公开内容涉及具有开路漏极的n沟道结场效应晶体管（NJFET）和/或ap沟道结场效应晶体管（PJFET），其中开路漏极允许晶体管在经历栅极漏电流之前以更高的电压工作 。 开路漏极允许电压增加几倍，而不增加晶体管的尺寸。 开放漏极基本上扩散了在器件的漏极处产生的相应电场的等势线，使得局部电场以及因此的冲击电离率被降低以将电流重新导向晶体管表面以下。
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公开(公告)号：US07498639B2
公开(公告)日：2009-03-03
申请号：US11233960
申请日：2005-09-23
IPC分类号： H01L31/112
CPC分类号： H01L27/0623 , H01L21/76229 , H01L21/8249 , H01L27/0207
摘要： An integrated BiCMOS semiconductor circuit has active moat areas in silicon. The active moat areas include electrically active components of the semiconductor circuit, which comprise active window structures for base and/or emitter windows. The integrated BiCMOS semiconductor circuit has zones where silicon is left to form dummy moat areas which do not include electrically active components, and has isolation trenches to separate the active moat areas from each other and from the dummy moat areas. The dummy moat areas comprise dummy window structures having geometrical dimensions and shapes similar to those of the active window structures for the base and/or emitter windows.
摘要翻译： 集成的BiCMOS半导体电路在硅中具有积极的护城河区域。 活动的护壕区域包括半导体电路的电活性部件，其包括用于基底和/或发射器窗口的有源窗口结构。 集成的BiCMOS半导体电路具有区域，其中硅留下以形成不包括电活性部件的虚拟护城河区域，并且具有隔离沟槽以将活动的护壕区域彼此分开并与虚拟的护城河区域分离。 虚拟护城河区域包括具有几何尺寸和形状的虚拟窗户结构，其类似于用于基座和/或发射器窗口的活动窗口结构的几何尺寸和形状。
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公开(公告)号：US20080042199A1
公开(公告)日：2008-02-21
申请号：US11504412
申请日：2006-08-15
IPC分类号： H01L27/12
CPC分类号： H01L29/808 , H01L29/0607 , H01L29/66901
摘要： The disclosure herein pertains to fashioning an n channel junction field effect transistor (NJFET) and/or a p channel junction field effect transistor (PJFET) with an open drain, where the open drain allows the transistors to operate at higher voltages before experiencing gate leakage current. The open drain allows the voltage to be increased several fold without increasing the size of the transistors. Opening the drain essentially spreads equipotential lines of respective electric fields developed at the drains of the devices so that the local electric fields, and hence the impact ionization rates are reduced to redirect current below the surface of the transistors.
摘要翻译： 本文的公开内容涉及具有开路漏极的n沟道结场效应晶体管（NJFET）和/或ap沟道结场效应晶体管（PJFET），其中开路漏极允许晶体管在经历栅极漏电流之前以更高的电压工作 。 开路漏极允许电压增加几倍，而不增加晶体管的尺寸。 开放漏极基本上扩散了在器件的漏极处产生的相应电场的等势线，使得局部电场以及因此的冲击电离率被降低以将电流重新导向晶体管表面以下。
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公开(公告)号：US07192838B2
公开(公告)日：2007-03-20
申请号：US10928655
申请日：2004-08-26
IPC分类号： H01L21/331
CPC分类号： H01L29/66242 , H01L21/82285 , H01L29/7378
摘要： Method of producing complementary SiGe bipolar transistors. In a method of producing complementary SiGe bipolar transistors, interface oxide layers (38, 58) for NPN and PNP emitters (44, 64), are separately formed and emitter polysilicon (40, 60) is separately patterned, allowing these layers to be optimized for the respective conductivity type.
摘要翻译： 制造互补SiGe双极晶体管的方法。 在制造互补SiGe双极晶体管的方法中，分别形成用于NPN和PNP发射极（44,64）的界面氧化物层（38,58），发射极多晶硅（40,60）被分开构图，允许这些层被优化 对于各自的导电类型。
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9.发明申请Control of phosphorus profile by carbon in-situ doping for high performance vertical PNP transistor 审中-公开通过碳原位掺杂控制磷分布，用于高性能垂直PNP晶体管公开(公告)号：US20050118771A1
公开(公告)日：2005-06-02
申请号：US10978074
申请日：2004-10-28
IPC分类号： H01L21/331 , H01L29/10 , H01L29/73 , H01L29/732 , H01L29/737 , H01L21/425 , H01L21/8222
CPC分类号： H01L29/66287 , H01L29/1004 , H01L29/66242 , H01L29/732 , H01L29/7378
摘要： A method of producing a vertical bipolar PNP transistor is disclosed. The phosphorous profile in the base layer is controlled. Carbon that is incorporated in the base layer in the vicinity of the base-collector junction suppresses the diffusion of phosphorous deeper than implanted in a subsequent thermal step. PNP transistors with a narrow phosphorous-doped base can thus be manufactured with a cut-off frequency increased from 23 GHz to 30 GHz.
摘要翻译： 公开了一种制造垂直双极PNP晶体管的方法。 控制基层中的磷分布。 在底部 - 集电极结附近并入基底层中的碳，抑制磷的扩散比在随后的热步骤中植入更深。 因此可以制造具有从23GHz至30GHz的截止频率的具有窄磷掺杂基极的PNP晶体管。
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10.发明申请Method of fabricating complementary bipolar transistors with SiGe base regions 有权用SiGe基极区制造互补双极晶体管的方法公开(公告)号：US20050014341A1
公开(公告)日：2005-01-20
申请号：US10822078
申请日：2004-04-08
申请人： Badih El-Kareh , Scott Balster , Philipp Steinmann , Thomas Scharnagl , Manfred Schiekofer , Carl Willis
发明人： Badih El-Kareh , Scott Balster , Philipp Steinmann , Thomas Scharnagl , Manfred Schiekofer , Carl Willis
IPC分类号： H01L21/331 , H01L21/8228
CPC分类号： H01L29/66242 , H01L21/82285
摘要： In a method of fabricating complementary bipolar transistors with SiGe base regions the base regions of the NPN and PNP transistors are formed one after the other over two collector regions 20, 14 by epitaxial deposition of crystalline silicon-germanium layers 32a, 36a. With this method the germanium profile of the SiGe layers can be freely selected for both NPN and PNP transistors in thus enabling complementary transistor performance to be optimized individually. The SiGe layers 32a, 36a can be doped with an n-type or p-type dopant during or after deposition of the silicon-germanium layers 32a, 36a.
摘要翻译： 在制造具有SiGe基极区域的互补双极晶体管的方法中，NPN和PNP晶体管的基极区域通过晶体硅 - 锗层32a，36a的外延沉积而在两个集电极区域20,14之间一个接一个地形成。 使用这种方法，可以自由地为NPN和PNP晶体管选择SiGe层的锗分布，从而可以单独优化互补晶体管的性能。 SiGe层32a，36a可以在硅 - 锗层32a，36a沉积期间或之后掺杂n型或p型掺杂剂。
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