公开(公告)号：US4065557A

公开(公告)日：1977-12-27

申请号：US704842

申请日：1976-07-13

申请人： Werner Frommer ,  Horst Gericke ,  Uwe Keup ,  Walter Puls ,  Delt Schmidt ,  Otto Wagner

发明人： Werner Frommer ,  Horst Gericke ,  Uwe Keup ,  Walter Puls ,  Delt Schmidt ,  Otto Wagner

IPC分类号： A23K1/16 ,  A23K1/18 ,  A23K1/22 ,  C07H15/22 ,  C12P19/28 ,  A61K31/71 ,  A61K31/715 ,  C12D13/04

CPC分类号： C12P19/28 ,  A23K20/163 ,  A23K50/15 ,  A23K50/30 ,  C07H15/22 ,  Y10S435/827 ,  Y10S435/839 ,  Y10S435/917

摘要： Glucopyranosyl and oligoglucosidyl derivatives of 4,6-bisdesoxy-4-(4,5,6-trihydroxy-3-hydroxymethylcyclohex-2-en-1-ylamino)-.alpha.-D-glucopyranose, which are inhibitors of glycoside hydrolases of the digestive tract, favorably improve the meat:fat ratio in animals in favor of a higher proportion of meat. A single amino-sugar or a mixture of amino-sugars can be formulated in combination with an edible carrier and fed to animals. A representative embodiment is a pig feedstuff in admixture with O-{4,6-bisdesoxy-4-[lS-(1,4,6/5)-4,5,6-trihydroxy-3-hydroxymethylcyclohex-2-en-1-ylamino]-.alpha.-D-glucopyranoxyl}-(1.fwdarw.4)-O-.alpha.-D-glucopyranosyl-(1.fwdarw.4)-D-glucopyranose.

摘要翻译： 4,6-双脱氧-4-（4,5,6-三羟基-3-羟甲基环己-2-烯-1-基氨基）-α-D-吡喃葡萄糖的吡喃葡萄糖基和低聚葡糖苷衍生物，它们是糖苷水解酶的抑制剂 消化道，有利于提高肉类：动物脂肪比例，有利于肉类的比例较高。 单一氨基糖或氨基糖的混合物可以与可食用的载体组合配制并喂给动物。 代表性的实施方案是与O- {4,6-双脱氧-4- [1S-（1,4,6 / 5）-4,5,6-三羟基-3-羟甲基环己基-2-烯的混合物的猪饲料 -1-基氨基]-α-D-吡喃葡萄糖基} - （1-> 4）-O-α-D-吡喃葡萄糖基 - （1-> 4）-D-吡喃葡萄糖。

公开(公告)号：US20050254317A1

公开(公告)日：2005-11-17

申请号：US10844301

申请日：2004-05-12

申请人： Yuen Chan ,  Timothy Charest ,  John Rawlins ,  Arthur Tuminaro ,  Jatinder Wadhwa ,  Otto Wagner

发明人： Yuen Chan ,  Timothy Charest ,  John Rawlins ,  Arthur Tuminaro ,  Jatinder Wadhwa ,  Otto Wagner

IPC分类号： G11C7/00 ,  G11C7/08 ,  G11C7/20

CPC分类号： G11C7/20 ,  G11C7/08 ,  G11C2207/065

摘要： A SRAM sense amplifier timing circuit provides various delay settings for the sense amplifier enable signal (sae) and the sense amplifier reset signal (rse) in order to allow critical timing adjustments to be made for early mode, late mode conditions by varying the timing or with of the sense amplifier output pulse. These timing adjustments are programmable using scan in bits.

摘要翻译： SRAM读出放大器定时电路为读出放大器使能信号（sae）和读出放大器复位信号（rse）提供了各种延迟设置，以便允许通过改变时序来对早期模式，晚期模式条件进行临界定时调整，或者 具有读出放大器的输出脉冲。 这些定时调整可以使用扫描位进行编程。

公开(公告)号：US5761147A

公开(公告)日：1998-06-02

申请号：US805531

申请日：1997-02-25

申请人： Heinrich Lindner ,  Peter Knott ,  Otto Wagner

发明人： Heinrich Lindner ,  Peter Knott ,  Otto Wagner

IPC分类号： G11C11/41 ,  G06F12/00 ,  G11C8/16 ,  G11C8/00

CPC分类号： G11C8/16

摘要： A virtual two-port memory structure with fast write-thru operation is proposed. The virtual two-port memory structure employs a single-port memory cell (200). Means for comparing (260) compare a read address AR with a write address AW and means (270) for writing data from the data input terminal (250) into the cell (200) are bypassing said data to the data output terminal (280) as well, such that a write-thru operation is enabled if the read address AR matches the write address AW. The data just written into the cell are immediately available as read data within the same cycle. The multiplex unit used in prior art solutions is no longer necessary, the delay caused by this device is omitted and the advantages of the virtual two-port cell requiring less chip space are maintained.

摘要翻译： 提出了具有快速写入操作的虚拟双端口存储器结构。 虚拟双端口存储器结构采用单端口存储单元（200）。 用于将读取地址AR与写入地址AW进行比较（260）的装置和用于将数据从数据输入端（250）写入单元（200）的装置（270）将所述数据旁路到数据输出端（280） 同样，如果读地址AR与写入地址AW匹配，则使能写入操作。 刚刚写入单元格的数据在同一周期内立即可用作读取数据。 现有技术解决方案中使用的多路复用单元不再需要，省略了由该设备引起的延迟，并且保持了需要较少芯片空间的虚拟双端口单元的优点。

公开(公告)号：US07755394B2

公开(公告)日：2010-07-13

申请号：US12196427

申请日：2008-08-22

申请人： Thomas Froehnel ,  Guenter Mayer ,  Rolf Sautter ,  Otto Wagner

发明人： Thomas Froehnel ,  Guenter Mayer ,  Rolf Sautter ,  Otto Wagner

IPC分类号： H03K19/0175

CPC分类号： H03K19/018521 ,  H03K19/0013

摘要： A circuit (01) combining level shift function with gated reset is described, performing a simple logic function with inputs supplied from a lower voltage (VD) and a drive out at its output (05) with a higher voltage (VC). Said circuit (01) comprises a gated reset scheme plus devices (10, 30, 40) for logic function.

摘要翻译： 描述了将电平移位功能与门控复位组合的电路（01），其具有由较低电压（VD）提供的输入和在其输出端（05）以较高电压（VC）驱动的简单逻辑功能。 所述电路（01）包括门控复位方案加上用于逻辑功能的装置（10,30,40）。

公开(公告)号：US07289370B2

公开(公告)日：2007-10-30

申请号：US11186606

申请日：2005-07-21

申请人： Chad Allen Adams ,  Anthony Gus Aipperspach ,  Juergen Pille ,  Otto Wagner

发明人： Chad Allen Adams ,  Anthony Gus Aipperspach ,  Juergen Pille ,  Otto Wagner

IPC分类号： G11C16/04

CPC分类号： G11C11/413 ,  G11C7/06 ,  G11C7/1006 ,  G11C7/12

摘要： In a first aspect, a first method is provided for accessing memory. The first method includes the steps of (1) storing a bit in a cell included in a memory having a plurality of cells arranged into rows and columns, wherein each cell includes a group of transistors adapted to both store the bit and affect a signal asserted during a read operation on a bit line coupled to the cell such that the affected signal matches a value of the bit stored in the cell; and (2) preventing the value of the bit stored in the cell from changing state while the group of transistors affects the signal asserted during the read operation on the bit line coupled to the cell. Numerous other aspects are provided.

公开(公告)号：US20070165447A1

公开(公告)日：2007-07-19

申请号：US11623443

申请日：2007-01-16

申请人： Otto Wagner ,  Sebastian Ehrenreich ,  Torsten Mahnke ,  Anthony Gus Aipperspach

发明人： Otto Wagner ,  Sebastian Ehrenreich ,  Torsten Mahnke ,  Anthony Gus Aipperspach

IPC分类号： G11C11/00

CPC分类号： G11C11/412

摘要： Asymmetrical random access memory cell (1) comprising cross coupled inverters (2, 3) which are driven at their nodes (22, 32) by separate bit-lines (blt, blc) of a pair of complementary bit-lines, which are connected via a pass-transistor (21, 31), wherein the random access memory cell is asymmetrical by means of the cross coupled inverters (2, 3) which have asymmetrically physical behaviours whereby different switching thresholds of the inverters are present, and that the pass-transistors (21, 31) are driven by separate controlled wordlines (wl, wwl). Furthermore the invention relates to a random access memory comprising a plurality of such asymmetrical random access memory cells and to a method to operate such a random access memory.

摘要翻译： 非对称随机存取存储单元（1）包括交叉耦合的反相器（2,3），它们通过一对互补位线的分开的位线（blt，blc）在其节点（22,32）处被驱动，所述位线连接 通过通过晶体管（21,31），其中随机存取存储单元通过具有不对称物理行为的交叉耦合反相器（2,3）不对称，从而存在逆变器的不同切换阈值，并且通过 - 晶体管（21,31）由单独的受控字线（w1，wwl）驱动。 此外，本发明涉及包括多个这样的非对称随机存取存储器单元的随机存取存储器和一种操作这样的随机存取存储器的方法。

公开(公告)号：US07535750B2

公开(公告)日：2009-05-19

申请号：US11623443

申请日：2007-01-16

申请人： Otto Wagner ,  Sebastian Ehrenreich ,  Torsten Mahnke ,  Anthony Gus Aipperspach

发明人： Otto Wagner ,  Sebastian Ehrenreich ,  Torsten Mahnke ,  Anthony Gus Aipperspach

IPC分类号： G11C11/00

CPC分类号： G11C11/412

摘要： Asymmetrical random access memory cell (1) including cross coupled inverters (2, 3) which are driven at their nodes (22, 32) by separate bit-lines (blt, blc) of a pair of complementary bit-lines, which are connected via a pass-transistor (21, 31), wherein the random access memory cell is asymmetrical by means of the cross coupled inverters (2, 3) which have asymmetrically physical behaviours whereby different switching thresholds of the inverters are present, and that the pass-transistors (21, 31) are driven by separate controlled wordlines (wl, wwl).

摘要翻译： 包括交叉耦合的反相器（2,3）的不对称随机存取存储器单元（1），它们通过一对互补位线的分开的位线（blt，blc）在它们的节点（22,32）处被驱动， 通过通过晶体管（21,31），其中随机存取存储单元通过具有不对称物理行为的交叉耦合反相器（2,3）不对称，从而存在逆变器的不同切换阈值，并且通过 - 晶体管（21,31）由单独的受控字线（w1，wwl）驱动。

公开(公告)号：US20070189061A1

公开(公告)日：2007-08-16

申请号：US11669369

申请日：2007-01-31

申请人： Stefan Buettner ,  Torsten Mahnke ,  Wolfgang Penth ,  Otto Wagner

发明人： Stefan Buettner ,  Torsten Mahnke ,  Wolfgang Penth ,  Otto Wagner

IPC分类号： G11C11/00

CPC分类号： G11C11/412

摘要： Asymmetrical random access memory cell, memory comprising asymmetrical memory cells and method to operate such a memory The invention relates to an asymmetrical random access memory cell (1) comprising cross coupled inverters (2, 3) which are driven at their nodes (22, 32) by separate bit-lines (b1t, b1c) of a pair of complementary bit-lines, which are connected via a pass-transistors (21, 31), wherein said cross coupled inverters (2, 3) have different switching thresholds and exhibit asymmetrical physical behaviours, wherein an additional pass-transistor (4) is provided in series to one of the pass-transistors (21) between one of the nodes (22) and its dedicated bit-line (blc). Further the invention relates to a random access memory comprising such memory cells and to a method of operating such a memory.

摘要翻译： 不对称随机存取存储器单元，包括不对称存储器单元的存储器和用于操作这种存储器的方法本发明涉及一种非对称随机存取存储单元（1），包括交叉耦合的反相器（2,3），它们在其节点（22,32） ）通过一对互补位线的分开的位线（b 1 t，b 1 c），其经由传输晶体管（21,31）连接，其中所述交叉耦合的反相器（2,3）具有不同的 切换阈值并表现出不对称的物理行为，其中附加的传输晶体管（4）与节点（22）中的一个与其专用位线（blc）之间的一个传输晶体管（21）串联提供。 此外，本发明涉及包括这种存储器单元的随机存取存储器以及操作这种存储器的方法。

公开(公告)号：US4815113A

公开(公告)日：1989-03-21

申请号：US110399

申请日：1987-10-20

申请人： Thomas Ludwig ,  Helmut Schettler ,  Otto Wagner ,  Rainer Zuhlke

发明人： Thomas Ludwig ,  Helmut Schettler ,  Otto Wagner ,  Rainer Zuhlke

IPC分类号： H03K4/02 ,  H03G11/00 ,  H03K5/02 ,  H03K6/04 ,  H03K17/16 ,  H03K19/0185 ,  H03K5/22

CPC分类号： H03K6/04 ,  H03G11/008 ,  H03K19/018557

摘要： A method for the digital slope control of the output signals of power amplifiers, as well as a power amplifier suitable for carrying out the method as described. One way of representing the actual slope value is via the number of clock pulses applied to a counter during a measuring interval which depends in its duration on the slope. Such a measuring interval is produced by applying the pulses of a ring oscillator containing one of the power amplifiers to another counter until the overflow of the latter. Another mode of representing the actual slope value consists in counting the number of pulses of the ring oscillator during a measuring interval of predetermined duration. Actual and nominal values of the slope are compared. The results of this comparison change the contents of a left/right-shift register. Its parallel outputs influence, via control lines, control inputs of the power amplifiers in order to alter their slope by switching on or off output transistors arranged in parallel with respect to their switching paths.

摘要翻译： 一种用于数字斜率控制功率放大器的输出信号的方法，以及适用于执行所述方法的功率放大器。 表示实际斜率值的一种方法是在测量间隔期间施加到计数器的时钟脉冲数，这取决于其在斜率上的持续时间。 这样的测量间隔是通过将包含功率放大器的环形振荡器的脉冲施加到另一个计数器而产生的，直到后者的溢出。 表示实际斜率值的另一模式在于在预定持续时间的测量间隔期间对环形振荡器的脉冲数进行计数。 比较斜率的实际值和标称值。 该比较的结果改变左/右移位寄存器的内容。 其并联输出通过控制线影响功率放大器的控制输入，以便通过接通或关闭相对于它们的开关路径并联布置的输出晶体管来改变其斜率。

公开(公告)号：US20080080259A1

公开(公告)日：2008-04-03

申请号：US11862235

申请日：2007-09-27

申请人： Stefan Buettner ,  Juergen Pille ,  Otto Wagner ,  Dieter Wendel

发明人： Stefan Buettner ,  Juergen Pille ,  Otto Wagner ,  Dieter Wendel

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C7/18

摘要： A method and memory circuit comprising a plurality of cells accessible by word lines and bit lines is described, wherein each cell includes a group of six transistors adapted to both store a bit inserted into the cell during a write operation and affect a signal asserted during a read operation on a bit line coupled to the cell such that the affected signal matches a value of the bit stored in the cell, wherein the word lines and bit lines of the memory are divided into sections assigned to groups of equal numbers of cells, wherein said sections are individually accessible for read or write operations such that one cell of a group can be read simultaneously while writing another cell of the group.

摘要翻译： 描述了包括由字线和位线可访问的多个单元的方法和存储器电路，其中每个单元包括一组六个晶体管，其适于在写操作期间存储插入到单元中的位，并且影响在 在耦合到该单元的位线上读取操作，使得受影响的信号与存储在单元中的位的值相匹配，其中存储器的字线和位线被分成分配给相同数量的单元的组，其中 所述部分可单独访问用于读取或写入操作，使得可以同时读取组中的一个单元同时写入该组的另一个单元。