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公开(公告)号：US11557346B2
公开(公告)日：2023-01-17
申请号：US17336314
申请日：2021-06-02
IPC分类号： G11C16/04 , G11C16/10 , G11C16/34 , H01L27/11582
摘要： Apparatuses and techniques are described for detecting and compensating for a set of memory cells having a slow program speed, based on a comparison between the number of program loops used to complete programming for different data states. A program loop (PL) number is stored when programming is completed for memory cells of each assigned data state. The PL number of an nth state is then compared to the PL number of another state such as the n−1st state. If the difference between the PL numbers exceeds a threshold, the set of memory cells is considered to be slow programming and a compensation is triggered. The compensation can involve increasing the program pulse width in each remaining program pulse of the program operation. In another approach, the compensation can be triggered and subsequently deactivated in the program operation.
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2.发明公开公开(公告)号：US20240006010A1
公开(公告)日：2024-01-04
申请号：US17856073
申请日：2022-07-01
发明人： Xuan Tian , Liang Li , Dandan Yi , Jojo Xing , Vincent Yin , Yongke Sun , Alan Bennett
CPC分类号： G11C29/42 , G11C29/4401 , G11C29/1201 , G11C2029/1202
摘要： In some situations, a leak on a wordline may be a localized problem that causes data loss in a block that contains the wordline. In other situations, such as when the leak occurs near a peripheral wordline routing area, the leak can affect the entire memory die. The storage system provided herein has a fatal wordline leak detector that determines the type of leak and, accordingly, whether just the block should be retired or whether related blocks should be retired.
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公开(公告)号：US20240114685A1
公开(公告)日：2024-04-04
申请号：US17954757
申请日：2022-09-28
发明人： Liang Li , Xuan Tian , Zhen Qin , Yanli Zhang , Yan Li
IPC分类号： H01L27/11582 , G11C16/04 , G11C16/30 , H01L27/11573
CPC分类号： H01L27/11582 , G11C16/0483 , G11C16/30 , H01L27/11573 , H01L27/11565
摘要： A stack of alternating layers of dielectric and conductive materials are formed on a substrate. A first portion of the stack of alternating layers forms a plurality of blocks of NAND memory. A second portion of the stack of alternating layers forms a configurable capacitor structure. The configurable capacitor structure is configurable to form one or more capacitors of configurable capacitance.
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4.发明授权公开(公告)号：US12099743B2
公开(公告)日：2024-09-24
申请号：US17709745
申请日：2022-03-31
发明人： Liang Li , Loc Tu , Yinfeng Yu , Xuan Tian
CPC分类号： G06F3/0655 , G06F3/0604 , G06F3/064 , G06F3/0653 , G06F3/0679 , G06N5/04
摘要： A non-volatile storage apparatus comprises a plurality of memory cells that store host data and two models, a control circuit for writing to and reading from the memory cells, and an inference circuit. The inference circuit uses the first model with a first set of one or more metrics describing current operation of the non-volatile storage apparatus to make a first level prediction about defects and uses the second model with a second set of one or more metrics describing current operation of the non-volatile storage apparatus to make a second level prediction about defects. In one embodiment, the first level prediction is faster to make and uses less data collection, but is not as reliable, as the second level prediction. While second level prediction is more reliable, it takes more time to perform and requires a more intensive data collection, so it is only used when needed.
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公开(公告)号：US20240296891A1
公开(公告)日：2024-09-05
申请号：US18358635
申请日：2023-07-25
CPC分类号： G11C16/16 , G11C16/0433 , G11C16/08 , G11C16/102
摘要： Technology is disclosed herein for programing memory cells with a post-program erase. In an aspect, the post-program erase includes a bit-level erase that only erases memory cells that are to remain in an erased state after the program operation. Memory cells that are to remain in programmed states may be inhibited from erase during the post-program erase. In an aspect, the post-program erase does not have an erase verify, which saves time and/or power. In an aspect, the post-program erase includes applying a single erase pulse, which saves time and/or power. In an aspect, the duration of the post-program erase pulse is shorter than an erase pulse used prior to programming, which saves time and/or power.
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公开(公告)号：US20240144996A1
公开(公告)日：2024-05-02
申请号：US18356774
申请日：2023-07-21
IPC分类号： G11C11/4096 , G11C11/408 , G11C11/4094
CPC分类号： G11C11/4096 , G11C11/4085 , G11C11/4094
摘要： Technology is disclosed herein compensating for neighbor memory cell interference on a target memory cell when reading the target memory cell. The voltage that is applied to the bit line associated with the target memory cell may have a magnitude that depends on the data state of the neighbor memory cell. The magnitude of the voltage on the bit line may impact the amount of drain-induced barrier lowering (DIBL) experienced by the target memory cell. The amount of DIBL may be used to provide a desired amount of compensation for the neighbor memory cell interference. A higher bit line voltage may be used to create a greater amount of DIBL and therefore greater amount of compensation for neighbor memory cell interference.
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7.发明公开公开(公告)号：US20230315330A1
公开(公告)日：2023-10-05
申请号：US17709745
申请日：2022-03-31
发明人： Liang Li , Loc Tu , Yinfeng Yu , Xuan Tian
CPC分类号： G06F3/0655 , G06F3/0604 , G06F3/0653 , G06F3/0679 , G06F3/064 , G06N5/04
摘要： A non-volatile storage apparatus comprises a plurality of memory cells that store host data and two models, a control circuit for writing to and reading from the memory cells, and an inference circuit. The inference circuit uses the first model with a first set of one or more metrics describing current operation of the non-volatile storage apparatus to make a first level prediction about defects and uses the second model with a second set of one or more metrics describing current operation of the non-volatile storage apparatus to make a second level prediction about defects. In one embodiment, the first level prediction is faster to make and uses less data collection, but is not as reliable, as the second level prediction. While second level prediction is more reliable, it takes more time to perform and requires a more intensive data collection, so it is only used when needed.
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公开(公告)号：US20220392534A1
公开(公告)日：2022-12-08
申请号：US17336314
申请日：2021-06-02
摘要： Apparatuses and techniques are described for detecting and compensating for a set of memory cells having a slow program speed, based on a comparison between the number of program loops used to complete programming for different data states. A program loop (PL) number is stored when programming is completed for memory cells of each assigned data state. The PL number of an nth state is then compared to the PL number of another state such as the n−1st state. If the difference between the PL numbers exceeds a threshold, the set of memory cells is considered to be slow programming and a compensation is triggered. The compensation can involve increasing the program pulse width in each remaining program pulse of the program operation. In another approach, the compensation can be triggered and subsequently deactivated in the program operation.
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公开(公告)号：US11367491B1
公开(公告)日：2022-06-21
申请号：US17213997
申请日：2021-03-26
发明人： Liang Li , Xuan Tian , Vincent Yin , Jiahui Yuan
摘要： Apparatuses and techniques are described for recovering from errors in a read operation. When a read operation results in an uncorrectable read error, recovery read operations are performed for each read voltage of a page of data. Each recovery read operation uses a different timing. The different timings can involve a time period which is allocated for a voltage transition, such as a settling time of a word line or bit line voltage, or a time allocated for an under kick or over kick of a word line or bit line voltage. An error count is obtained for each different timing, and an optimum timing is determined based on the lowest error count. A retry read operation is performed in which an optimum timing is used for the voltage transition for each read voltage of the page.
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