-
公开(公告)号：US20240282363A1
公开(公告)日：2024-08-22
申请号：US18225344
申请日：2023-07-24
发明人： Albert Chen , Jiahui Yuan , Sarath Puthenthermadam , Akira Okada
IPC分类号： G11C11/4096 , G11C11/4076 , G11C11/408
CPC分类号： G11C11/4096 , G11C11/4076 , G11C11/4085
摘要： A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to one of a plurality of word lines and disposed in memory holes each coupled to one of a plurality of bit lines. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the plurality of word lines and the memory holes and is configured to read the memory cells in a read operation. The control means is also configured to adjust at least one word line read timing and ramping parameter used during the read operation based on an amount of cycling of the memory cells.
-
公开(公告)号：US20240282358A1
公开(公告)日：2024-08-22
申请号：US18224839
申请日：2023-07-21
发明人： Yi Song , Jiahui Yuan , Deepanshu Dutta
IPC分类号： G11C11/408 , G11C5/14 , G11C11/4096
CPC分类号： G11C11/4085 , G11C5/145 , G11C11/4096
摘要： A storage device is disclosed. The storage device is configured to: determine data states for a first set of memory cells of a first neighboring word line of the and a second set of memory cells of a second neighboring word line, the first and the second neighboring word lines being adjacent to a selected word line; identify a zone of a plurality of zones for each data state combination of the data states, each data state combination comprising a data state of a memory cell of the first set of memory cells and a data state of a memory cell of the second set of memory cells, each zone of the plurality of zones corresponding to a bit line clamping voltage; and perform a read operation on the selected word line including applying each bit line clamping voltage corresponding to any zones identified.
-
公开(公告)号：US11657883B2
公开(公告)日：2023-05-23
申请号：US17382424
申请日：2021-07-22
发明人： Ke Zhang , Liang Li , Jiahui Yuan
CPC分类号： G11C16/3445 , G11C16/08 , G11C16/102 , G11C16/26 , G11C16/3459
摘要： Apparatuses and techniques are described for detecting and isolating defective blocks of memory cells in a multi-plane operation such as program or erase. In one aspect, a program operation begins in a multi-plane mode, for one block in each plane. If fewer than all blocks complete programming by the time a trigger number of program loops have been performed, one or more unpassed blocks are programmed further, one at a time, in a single plane mode. If the one or more unpassed blocks do not complete programming when a maximum allowable number of program loops have been performed, they are marked as bad blocks and disabled from further operations. In another aspect, when a trigger number of program loops have been performed, one or more unpassed blocks are subject to a word line leakage detection operation.
-
公开(公告)号：US20240055063A1
公开(公告)日：2024-02-15
申请号：US17886155
申请日：2022-08-11
发明人： Sarath Puthenthermadam , Longju Liu , Parth Amin , Sujjatul Islam , Jiahui Yuan
CPC分类号： G11C29/12005 , G11C16/0483 , G11C16/10 , G11C16/16 , G11C2029/1202
摘要： Technology is disclosed herein for detecting grown bad blocks in a non-volatile storage system. A stress test may accelerate stressful conditions on the memory cells and thereby provide for early detection of grown bad blocks. The stress test may include applying a program voltage to a selected word line and a stress voltage that is less than a nominal boosting voltage to a word line adjacent one side of the selected word line. The combination of the program voltage and the stress voltage may generate an e-field that is stronger than an e-field that would be generated in a normal program operation, thereby accelerating the stress on the memory cells. The stress test mat further include programming all of the memory cells to a relatively high threshold voltage, which may create additional stress on the memory cells.
-
公开(公告)号：US20230048326A1
公开(公告)日：2023-02-16
申请号：US17400609
申请日：2021-08-12
发明人： Liang Li , Qianqian Yu , Jiahui Yuan , Loc Tu
摘要： Apparatuses and techniques are described for obtaining a threshold voltage distribution for a set of memory cells based on a user read mode. The user read mode can be based on various factors including a coding of a page and an increasing or decreasing order of the read voltages. The read process for the Vth distribution is made to mimic the read mode which is used when the memory device is in the hands of the end user. This results in a Vth distribution which reflects the user's experience to facilitate troubleshooting. In some cases, one or more dummy read operations are performed, where the read result is discarded, prior to a read operation which is used to build the Vth distribution.
-
公开(公告)号：US11367491B1
公开(公告)日：2022-06-21
申请号：US17213997
申请日：2021-03-26
发明人： Liang Li , Xuan Tian , Vincent Yin , Jiahui Yuan
摘要： Apparatuses and techniques are described for recovering from errors in a read operation. When a read operation results in an uncorrectable read error, recovery read operations are performed for each read voltage of a page of data. Each recovery read operation uses a different timing. The different timings can involve a time period which is allocated for a voltage transition, such as a settling time of a word line or bit line voltage, or a time allocated for an under kick or over kick of a word line or bit line voltage. An error count is obtained for each different timing, and an optimum timing is determined based on the lowest error count. A retry read operation is performed in which an optimum timing is used for the voltage transition for each read voltage of the page.
-
公开(公告)号：US11967388B2
公开(公告)日：2024-04-23
申请号：US17886155
申请日：2022-08-11
发明人： Sarath Puthenthermadam , Longju Liu , Parth Amin , Sujjatul Islam , Jiahui Yuan
CPC分类号： G11C29/12005 , G11C16/0483 , G11C16/10 , G11C16/16 , G11C2029/1202
摘要： Technology is disclosed herein for detecting grown bad blocks in a non-volatile storage system. A stress test may accelerate stressful conditions on the memory cells and thereby provide for early detection of grown bad blocks. The stress test may include applying a program voltage to a selected word line and a stress voltage that is less than a nominal boosting voltage to a word line adjacent one side of the selected word line. The combination of the program voltage and the stress voltage may generate an e-field that is stronger than an e-field that would be generated in a normal program operation, thereby accelerating the stress on the memory cells. The stress test mat further include programming all of the memory cells to a relatively high threshold voltage, which may create additional stress on the memory cells.
-
公开(公告)号：US20230343395A1
公开(公告)日：2023-10-26
申请号：US17726923
申请日：2022-04-22
发明人： Ke Zhang , Liang Li , Jiahui Yuan
CPC分类号： G11C16/08 , G11C16/12 , G11C16/107
摘要： A non-volatile memory system includes a control circuit connected to non-volatile memory cells. The control circuit is configured to concurrently program memory cells connected to different word lines that are in different sub-blocks of different blocks in different planes of a die.
-
公开(公告)号：US11790994B2
公开(公告)日：2023-10-17
申请号：US17481575
申请日：2021-09-22
发明人： Ming Wang , Liang Li , Jiahui Yuan
CPC分类号： G11C16/102 , G11C16/08 , G11C16/26 , G11C16/30
摘要： A memory system separately programs memory cells connected by a common word line to multiple sets of data states with the set of data states having higher threshold voltage data states being programmed before the set of data states having lower threshold voltage data states. The memory system also separately programs memory cells connected by an adjacent word line to the multiple sets of data states such that memory cells connected by the adjacent word line are programmed to higher data states after memory cells connected by the common word line are programmed to higher data states and prior to memory cells connected by the common word line are programmed to lower data states.
-
公开(公告)号：US20230023618A1
公开(公告)日：2023-01-26
申请号：US17382424
申请日：2021-07-22
发明人： Ke Zhang , Liang Li , Jiahui Yuan
摘要： Apparatuses and techniques are described for detecting and isolating defective blocks of memory cells in a multi-plane operation such as program or erase. In one aspect, a program operation begins in a multi-plane mode, for one block in each plane. If fewer than all blocks complete programming by the time a trigger number of program loops have been performed, one or more unpassed blocks are programmed further, one at a time, in a single plane mode. If the one or more unpassed blocks do not complete programming when a maximum allowable number of program loops have been performed, they are marked as bad blocks and disabled from further operations. In another aspect, when a trigger number of program loops have been performed, one or more unpassed blocks are subject to a word line leakage detection operation.
-
-
-
-
-
-
-
-
-
搜索结果
15 条记录 (耗时 0.023 秒)
