公开(公告)号：US20050060629A1

公开(公告)日：2005-03-17

申请号：US10660032

申请日：2003-09-11

申请人： William Cochran ,  William Hovis ,  Randall Jensen

发明人： William Cochran ,  William Hovis ,  Randall Jensen

IPC分类号： G01R31/317 ,  H03M13/00

CPC分类号： G01R31/31715

摘要： A method and apparatus are provided for implementing a redundancy enhanced differential signal interface. A differential signaling I/O pair is coupled to a differential receiver interface. The differential receiver interface includes a pair of multiplexers coupled to a differential receiver. An error detecting mechanism is coupled to the differential receiver for detecting an error. When an error is detected, an interface operating speed is reduced. True and complement sides of a differential signaling I/O pair are alternately tested by first enabling a multiplexer control of one of the multiplexers, reading data, and checking for the error; then enabling a multiplexer control of the other multiplexer, reading data, and checking for the error. Responsive to detecting a failure of a true side or a complement side, the detected failed true side or complement side is set to a reference voltage and the reduced interface operating speed is maintained for continued operation.

摘要翻译： 提供了一种用于实现冗余增强的差分信号接口的方法和装置。 差分信号I / O对耦合到差分接收器接口。 差分接收器接口包括耦合到差分接收器的一对多路复用器。 误差检测机构耦合到差分接收器，用于检测误差。 当检测到错误时，界面操作速度降低。 通过首先启用多路复用器之一的多路复用器控制，读取数据和检查错误来交替测试差分信号I / O对的真和补码侧; 然后启用另一个多路复用器的多路复用器控制，读取数据和检查错误。 响应于检测真实侧或补偿侧的故障，检测到的失败的真实侧或补偿侧被设置为参考电压，并且维持降低的接口操作速度以继续操作。

公开(公告)号：US20060109726A1

公开(公告)日：2006-05-25

申请号：US10994087

申请日：2004-11-19

申请人： William Cochran ,  William Hovis

发明人： William Cochran ,  William Hovis

IPC分类号： G11C29/00

CPC分类号： G11C29/14 ,  G11C11/401 ,  G11C29/18

摘要： A method, apparatus, and computer program product are provided for implementing an enhanced DRAM interface checking. An interface check mode enables interface checking using a refresh command for a DRAM. A predefined address pattern is provided for the interface address inputs during a refresh command cycle. Interface address inputs are checked for a proper value being applied and an error is signaled for unexpected results. An extended test mode includes further testing during a cycle after the refresh command cycle. Then command inputs also are checked for a proper value being applied and an error is signaled for unexpected results.

摘要翻译： 提供了一种用于实现增强的DRAM接口检查的方法，装置和计算机程序产品。 接口检查模式使用DRAM的刷新命令进行接口检查。 在刷新命令循环期间为接口地址输入提供预定义的地址模式。 检查接口地址输入是否正在应用值，并发出错误信号，以获取意外结果。 扩展测试模式包括在刷新命令周期之后的一个周期内的进一步测试。 然后，还将检查命令输入是否正在应用值，并发出错误信号，以获得意外结果。

公开(公告)号：US20060090112A1

公开(公告)日：2006-04-27

申请号：US10961745

申请日：2004-10-08

申请人： William Cochran ,  William Hovis ,  Paul Rudrud

发明人： William Cochran ,  William Hovis ,  Paul Rudrud

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G06F12/0804 ,  G06F12/084

摘要： Verification operations are utilized to effectively verify multiple associated write operations. A verification operation may be initiated after the issuance of a plurality of write operations that initiate the storage of data to a memory storage device, and may be configured to verify only a subset of the data written to the memory storage device by the plurality of write operations. As a result, verification operations are not required to be performed after each write operation, and consequently, the number of verification operations, and thus the processing and communication bandwidth consumed thereby, can be substantially reduced.

公开(公告)号：US20060129899A1

公开(公告)日：2006-06-15

申请号：US11013150

申请日：2004-12-15

申请人： William Cochran ,  William Hovis

发明人： William Cochran ,  William Hovis

IPC分类号： G11C29/00

CPC分类号： G06F11/106 ,  G11C29/806 ,  G11C2029/0409

摘要： Redundant capacity in a memory system is utilized to facilitate active monitoring of solid state memory devices in the memory system. All or part of the data stored in an active solid state memory device, and used in an active data processing system, may be copied to at least one redundant memory device, e.g., by transitioning a memory address range that was allocated to the active memory device to the redundant memory device. By doing so, memory access requests for the memory address range, which would normally be directed to the active memory device, may instead be directed to the redundant memory device, thus enabling the active memory device to be tested (e.g., via writing and reading test data patterns to the active memory device) without interrupting system access to that memory address range.

摘要翻译： 利用存储器系统中的冗余容量来促进对存储器系统中的固态存储器件的主动监视。 存储在活动固态存储设备中并在活动数据处理系统中使用的数据的全部或部分数据可被复制到至少一个冗余存储器设备，例如通过转换分配给活动存储器的存储器地址范围 设备到冗余存储设备。 通过这样做，存储器地址范围的存储器访问请求通常被定向到活动存储器设备，可以被引导到冗余存储器设备，从而使活动存储器件能够被测试（例如，通过写入和读取 测试数据模式到活动存储设备），而不会中断对该存储器地址范围的系统访问。

公开(公告)号：US20050081125A1

公开(公告)日：2005-04-14

申请号：US10675420

申请日：2003-09-30

申请人： William Cochran ,  William Hovis

发明人： William Cochran ,  William Hovis

IPC分类号： G06F11/00 ,  G06F11/20

CPC分类号： G06F11/1666 ,  G06F11/20 ,  G06F11/2007 ,  G11C29/846

摘要： A method and apparatus for correcting internally defective devices by routing signals on an I/O line to a spare internal network. Such devices enable a system designer to substitute good internal networks, e.g., memory arrays, for failing internal networks without loss of functionality at the I/O level. A device includes a plurality of I/O lines, a plurality of internal networks, a plurality of multiplexers for routing signals from the individual I/O lines to the individual internal networks, and a multiplex controller for controlling the signal routing. Routing can be performed using multiplexers that operatively interconnect any I/O line with any internal network, multiplexers that shift signals on an I/O line to and adjacent internal network, and/or multiplexers that can shift signals on an I/O through a multiplexer to any other multiplexer, and then to any internal network.

摘要翻译： 一种用于通过将I / O线路上的信号路由到备用内部网络来校正内部缺陷设备的方法和装置。 这样的设备使得系统设计者能够将良好的内部网络（例如，存储器阵列）替换为内部网络发生故障，而不会在I / O级别丢失功能。 一种设备包括多个I / O线路，多个内部网络，用于将信号从各个I / O线路路由到各个内部网络的多路复用器，以及用于控制信号路由的多路复用控制器。 可以使用将任何I / O线与任何内部网络可操作地互连的多路复用器，将I / O线上的信号转换到相邻内部网络的多路复用器和/或可以通过I / O线路移位I / O上的信号的多路复用器来执行路由。 多路复用器到任何其他多路复用器，然后到任何内部网络。

公开(公告)号：US20050229060A1

公开(公告)日：2005-10-13

申请号：US10815248

申请日：2004-03-31

申请人： William Cochran ,  William Hovis

发明人： William Cochran ,  William Hovis

IPC分类号： G01R31/28 ,  G01R31/3185 ,  G11C17/00 ,  G11C29/14 ,  G11C29/50

CPC分类号： G11C29/50012 ,  G01R31/318516 ,  G11C29/14 ,  G11C29/50 ,  G11C2029/5004

摘要： A method and apparatus are provided for detecting degradation, such as, array degradation and logic degradation, in integrated circuits (ICs) including, for example, application specific integrated circuits (ASICs). A monitor built-in self-test (MBIST) engine is provided. At least one monitor element is coupled to the MBIST engine and is defined by predefined circuit elements in the integrated circuit. The MBIST engine is used for controlling operation of at least one monitor element for communicating with monitor bits to identify degradation of signal, timing and voltage margins.

摘要翻译： 提供了一种用于在包括例如专用集成电路（ASIC）的集成电路（IC）中检测诸如阵列退化和逻辑劣化的劣化的方法和装置。 提供监视器内置自检（MBIST）引擎。 至少一个监视器元件耦合到MBIST引擎，并且由集成电路中的预定义的电路元件来定义。 MBIST引擎用于控制至少一个监视元件的操作，用于与监视位进行通信，以识别信号的劣化，定时和电压裕度。

公开(公告)号：US20060268519A1

公开(公告)日：2006-11-30

申请号：US11138939

申请日：2005-05-26

申请人： Gerald Bartley ,  John Borkenhagen ,  William Cochran ,  William Hovis ,  Paul Rudrud

发明人： Gerald Bartley ,  John Borkenhagen ,  William Cochran ,  William Hovis ,  Paul Rudrud

IPC分类号： H05K7/20 ,  F28F7/00

CPC分类号： H01L25/105 ,  H01L25/18 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/0002 ,  H01L2924/1627 ,  H01L2924/00

摘要： A method and structure are provided for implementing enhanced cooling of a plurality of memory devices. The memory structure includes a stack of platters. A sub-plurality of memory devices is mounted on each platter. At least one connector is provided with each platter for connecting to the sub-plurality of memory devices. A heat sink is associated with the stack of platters for cooling the plurality of memory devices.

摘要翻译： 提供了一种用于实现多个存储器件的增强冷却的方法和结构。 存储器结构包括堆叠的盘片。 每个盘片上安装有多个存储器件。 至少一个连接器设置有每个盘片，用于连接到子多个存储器件。 散热器与用于冷却多个存储器件的盘堆相关联。

公开(公告)号：US20060106984A1

公开(公告)日：2006-05-18

申请号：US10992443

申请日：2004-11-18

申请人： Gerald Bartley ,  John Borkenhagen ,  William Cochran ,  William Hovis ,  Paul Rudrud

发明人： Gerald Bartley ,  John Borkenhagen ,  William Cochran ,  William Hovis ,  Paul Rudrud

IPC分类号： G06F12/00

CPC分类号： G06F12/08 ,  G06F12/0866 ,  G06F2212/205 ,  Y02D10/13

摘要： In a first aspect, a first method is provided for efficient memory usage. The first method includes the steps of (1) determining whether data retrieved from a first storage device is characterized as data that is primarily read; and (2) if data retrieved from the first storage device is characterized as data that is primarily read (a) writing the retrieved data in a temporary storage device with short write latency; and (b) writing the retrieved data in a high-density memory. Numerous other aspects are provided.

摘要翻译： 在第一方面，提供了一种有效的存储器使用的第一种方法。 第一种方法包括以下步骤：（1）确定从第一存储设备检索的数据是否被表征为主要被读取的数据; （2）如果从第一存储设备检索的数据被表征为主要读取的数据（a）将检索的数据写入具有短写入延迟的临时存储设备中; 和（b）将检索的数据写入高密度存储器。 提供了许多其他方面。

公开(公告)号：US20080102627A1

公开(公告)日：2008-05-01

申请号：US11876230

申请日：2007-10-22

申请人： Todd Christensen ,  Richard Donze ,  William Hovis ,  Terrance Kueper ,  John Sheets

发明人： Todd Christensen ,  Richard Donze ,  William Hovis ,  Terrance Kueper ,  John Sheets

IPC分类号： H01L21/44

CPC分类号： H01L21/28518 ,  H01L21/76889 ,  H01L21/76895 ,  H01L29/458 ,  H01L29/785

摘要： An apparatus and method are disclosed for an improved semiconductor interconnect scheme using a simplified process. In an embodiment of the apparatus, a polysilicon shape is formed on a silicon area. The polysilicon shape is created having a bridging vertex. When a spacer is created on the polysilicon shape, the spacer width is formed to be small enough near the bridging vertex to allow a silicide bridge to form that creates an electrical coupling between the silicon area and the bridging vertex. Semiconductor devices and circuits are created using the improved semiconductor interconnect scheme using the simplified process.

公开(公告)号：US20080093683A1

公开(公告)日：2008-04-24

申请号：US11876379

申请日：2007-10-22

申请人： Todd Christensen ,  Richard Donze ,  William Hovis ,  Terrance Kueper ,  John Sheets

发明人： Todd Christensen ,  Richard Donze ,  William Hovis ,  Terrance Kueper ,  John Sheets

IPC分类号： H01L29/78

CPC分类号： H01L21/28518 ,  H01L21/76889 ,  H01L21/76895 ,  H01L29/458 ,  H01L29/785

摘要： An apparatus and method are disclosed for an improved semiconductor interconnect scheme using a simplified process. In an embodiment of the apparatus, a polysilicon shape is formed on a silicon area. The polysilicon shape is created having a bridging vertex. When a spacer is created on the polysilicon shape, the spacer width is formed to be small enough near the bridging vertex to allow a silicide bridge to form that creates an electrical coupling between the silicon area and the bridging vertex. Semiconductor devices and circuits are created using the improved semiconductor interconnect scheme using the simplified process.

摘要翻译： 公开了一种使用简化过程的改进的半导体互连方案的装置和方法。 在该装置的实施例中，在硅区域上形成多晶硅形状。 产生具有桥接顶点的多晶硅形状。 当在多晶硅形状上形成间隔物时，在桥接顶点附近形成足够小的间隔物宽度，以形成硅化物桥，从而在硅区域和桥接顶点之间产生电耦合。 使用简化的工艺使用改进的半导体互连方案创建半导体器件和电路。