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公开(公告)号：US5047827A
公开(公告)日：1991-09-10
申请号：US569690
申请日：1990-08-20
IPC分类号： H01L21/265 , H01L21/822 , H01L27/04 , H01L27/08
CPC分类号： H01L27/0802
摘要： A high value, precision resistor (10) includes a doped region (18) having a boustrophedonic (folded or meandering) shape formed in a substrate (12). At least one section of the doped region (18) is formed by implantation using a focused ion beam. Where the entire doped region (18) is formed by the focused ion beam, the length thereof is selected to be large (10 to 100 times the width of the boustrophedonic shape) to maximize the accuracy of the resistor (10) by averaging over variations in grain size and implant dose. Alternatively, a probe resistor (32) and a plurality of similar unconnected doped sections (28) may be formed by means such as photolithography and flood ion implantation. The probe resistor (32) is measured at the desired operating temperature to determine the ratio of the measured resistance to the desired design resistance value. The unconnected doped sections (28) are then interconnected by plugs (40, 42, 44, 46), formed with a focussed ion beam, to program the fabricated resistor to exactly the designed resistance value at the desired operating temperature.
摘要翻译： 高价值的精密电阻器（10）包括在衬底（12）中形成的具有麻醉（折叠或曲折）形状的掺杂区域（18）。 通过使用聚焦离子束的注入形成掺杂区域（18）的至少一个部分。 在整个掺杂区域（18）由聚焦离子束形成的情况下，其长度被选择为较大的（10至100倍的波形形状的宽度），以使电阻器（10）的精度通过对变化的平均值来最大化 粒度和植入剂量。 或者，探针电阻器（32）和多个类似的未连接的掺杂部分（28）可以通过诸如光刻和泛洪离子注入的方式形成。 在期望的工作温度下测量探针电阻（32），以确定所测量的电阻与期望的设计电阻值之比。 然后，通过形成有聚焦离子束的插头（40,42,44,46）将未连接的掺杂部分（28）互连，以将所制造的电阻器精确地编程在所需工作温度下的设计电阻值。
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2.发明授权Programmable connection and isolation of active regions in an integrated circuit using ambiguous features to confuse a reverse engineer 失效使用模糊特征对集成电路中的有源区域进行可编程连接和隔离，从而使反向工程师混淆公开(公告)号：US08168487B2
公开(公告)日：2012-05-01
申请号：US11855005
申请日：2007-09-13
IPC分类号： H01L21/335
CPC分类号： H01L27/0203 , H01L23/573 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A technique for and structures for camouflaging an integrated circuit structure and strengthen its resistance to reverse engineering. A plurality of transistors are formed in a semiconductor substrate, at least some of the transistors being of the type having sidewall spacers with LDD regions formed under the sidewall spacers. Transistors are programmably interconnected with ambiguous interconnection features, the ambiguous interconnection features each comprising a channel formed in the semiconductor substrate with preferably the same dopant density as the LDD regions, with selected ones of the channels being formed of a conductivity type supporting electrical communication between interconnected active regions and with other selected ones of the channels being formed of a conductivity type inhibiting electrical communication but ambiguously appearing to a reverse engineer as supporting electrical communication.
摘要翻译： 用于伪装集成电路结构的技术和结构，并加强其对逆向工程的抵抗力。 在半导体衬底中形成多个晶体管，至少一些晶体管是具有侧壁间隔物的类型，其中LDD区形成在侧壁间隔物下。 晶体管可编程地与不明确的互连特征相互连接，这些不明确的互连特征各自包括形成在半导体衬底中的通道，其优选地与LDD区域具有相同的掺杂剂密度，其中选定的通道由导电类型形成，支持互连 有源区域和其它选择的通道由导电类型抑制电气通信形成，但是对于逆向工程师而言，这些通道似乎是支持电气通信。
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3.发明授权Cryptographic architecture with random instruction masking to thwart differential power analysis 有权具有随机指令掩码的加密架构，以阻止差分功率分析公开(公告)号：US08065532B2
公开(公告)日：2011-11-22
申请号：US10864569
申请日：2004-06-08
CPC分类号： G06F9/30101 , G06F9/3001 , G06F9/30181 , G06F9/321 , G06F9/3836 , G06F21/72 , G06F21/75 , G06F21/755 , G06F21/85 , G06F2221/2123 , H04L9/003 , H04L9/0625 , H04L2209/08 , H04L2209/12
摘要： An apparatus and method for preventing information leakage attacks that utilize timeline alignment. The apparatus and method inserts a random number of instructions into an encryption algorithm such that the leaked information can not be aligned in time to allow an attacker to break the encryption.
摘要翻译： 一种用于防止利用时间线对准的信息泄漏攻击的装置和方法。 该装置和方法将随机数量的指令插入到加密算法中，使得泄露的信息不能及时对准以允许攻击者中断加密。
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4.发明授权Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact 失效永久性地使用采用双重多晶硅层CMOS工艺的埋入触点实现晶体管公开(公告)号：US06740942B2
公开(公告)日：2004-05-25
申请号：US09882892
申请日：2001-06-15
IPC分类号： H01L2976
CPC分类号： H01L27/0203 , H01L21/76895 , H01L21/823462 , H01L23/576 , H01L27/0883 , H01L29/7834 , H01L2924/0002 , Y10S257/922 , H01L2924/00
摘要： A permanently-ON MOS transistor comprises silicon source and drain regions of a first conductivity type in a silicon well region of a second conductivity type. A silicon contact region of the first conductivity types is buried in the well region, said contact region contacting said source region and said drain region. A first gate insulating layer is selectively placed over the silicon source and drain regions. A second gate insulating layer is selectively placed over the first gate insulating layer and over the silicon contact region. A polysilicon gate region is placed over the second gate insulating layer.
摘要翻译： 永久导通MOS晶体管包括在第二导电类型的硅阱区域中的第一导电类型的硅源极和漏极区域。 所述第一导电类型的硅接触区域埋在所述阱区域中，所述接触区域接触所述源极区域和所述漏极区域。 选择性地将第一栅极绝缘层放置在硅源极和漏极区域上。 第二栅极绝缘层选择性地放置在第一栅极绝缘层上方和硅接触区域上。 多晶硅栅极区域放置在第二栅极绝缘层上。
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公开(公告)号：US5006715A
公开(公告)日：1991-04-09
申请号：US352440
申请日：1989-05-16
IPC分类号： H01J27/26
CPC分类号： H01J27/26
摘要： An ion evaporation source for tin ions is prepared by coating a source element with a wettability enhancing gallium coating, and then loading the source with tin. The tin may be the naturally occurring tin, but can be an enriched tin containing a higher concentration of Sn.sup.120. The source produces a beam having a high fraction of Sn.sup.+ and Sn.sup.++ ions, and a small amount of the ionized wettability coating material. All but the desired ions are readily separated from the beam.
摘要翻译： 通过涂覆具有润湿性增强镓涂层的源元件，然后用锡负载源来制备用于锡离子的离子蒸发源。 锡可以是天然存在的锡，但可以是含有较高浓度Sn120的富集锡。 该源产生具有高分数的Sn +和Sn ++离子的束，以及少量的电离润湿性涂层材料。 除了所需的离子之外，所有离子都容易与光束分离。
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公开(公告)号：US4967250A
公开(公告)日：1990-10-30
申请号：US426481
申请日：1989-10-23
IPC分类号： H01L29/10
CPC分类号： H01L29/1062
摘要： A charge-coupled device (CCD) is provided with a dopant implant gradient, lateral channel stops and blocking implants by means of a focused ion beam (FIB). The FIB is repeatedly scanned across each cell of the CCD as a succession of overlapping but discrete implant scans. The doping levels of the FIB implants accumulate to a stepwise approximation of a desired dopant density profile, the widths of the steps being no greater than about half the widths of the discrete FIB implants. With a FIB pixel of about 750-1,500 Angstroms, the widths of the steps are preferably about 250-500 Angstroms; the dimension of the cells in the dopant gradient direction can be made less than about 5 microns. The lateral channel stops and back blocking implants can be as narrow as single FIB pixel widths, thus freeing up more of the cell for charge carrying capacity.
摘要翻译： 电荷耦合器件（CCD）具有掺杂剂注入梯度，侧向通道通过聚焦离子束（FIB）停止和阻塞植入物。 FIB被重复地扫描在CCD的每个单元上，作为一系列重叠但离散的植入物扫描。 FIB植入物的掺杂水平累积到期望掺杂剂密度分布的逐步近似，步长的宽度不大于离散FIB植入物的宽度的大约一半。 具有约750-1,500埃的FIB像素，步长的宽度优选为约250-500埃; 可以使掺杂剂梯度方向上的单元的尺寸小于约5微米。 横向通道停止，背部阻挡植入物可以与单个FIB像素宽度一样窄，从而释放出更多的电池用于充电容量。
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7.发明授权Conductive channel pseudo block process and circuit to inhibit reverse engineering 失效导电通道伪块处理和电路抑制反向工程公开(公告)号：US08258583B1
公开(公告)日：2012-09-04
申请号：US12949657
申请日：2010-11-18
IPC分类号： H01L27/088
CPC分类号： H01L27/0203 , G06K19/073 , G06K19/07363 , H01L23/573 , H01L2924/0002 , H01L2924/00
摘要： A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having a controlled outline. A layer of conductive material having a controlled outline is disposed among said plurality of layers to provide artifact edges of the conductive material that resemble one type of transistor (operable vs. non-operable), when in fact another type of transistor was used.
摘要翻译： 用于伪装集成电路结构的技术和结构。 集成电路结构由具有受控轮廓的多层材料形成。 具有受控轮廓的导电材料层设置在所述多个层中，以提供类似于一种类型的晶体管（可操作与不可操作的）的导电材料的伪影边缘，当实际上使用另一种类型的晶体管时。
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8.发明授权公开(公告)号：US07935603B1
公开(公告)日：2011-05-03
申请号：US11807896
申请日：2007-05-29
IPC分类号： H01L21/336
CPC分类号： H01L21/823814 , H01L23/573 , H01L27/0203 , Y10S257/90
摘要： A technique for and structures for camouflaging an integrated circuit structure. The technique including forming active areas of a first conductivity type and LDD regions of a second conductivity type resulting in a transistor that is always non-operational when standard voltages are applied to the device.
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9.发明授权Conductive channel pseudo block process and circuit to inhibit reverse engineering 有权导电通道伪块处理和电路抑制逆向工程公开(公告)号：US07888213B2
公开(公告)日：2011-02-15
申请号：US11375846
申请日：2006-03-14
IPC分类号： H01L21/8236
CPC分类号： H01L27/0203 , G06K19/073 , G06K19/07363 , H01L23/573 , H01L2924/0002 , H01L2924/00
摘要： A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having a controlled outline. A layer of conductive material having a controlled outline is disposed among said plurality of layers to provide artifact edges of the conductive material that resemble one type of transistor (operable vs. non-operable), when in fact another type of transistor was used.
摘要翻译： 用于伪装集成电路结构的技术和结构。 集成电路结构由具有受控轮廓的多层材料形成。 具有受控轮廓的导电材料层设置在所述多个层中，以提供类似于一种类型的晶体管（可操作与不可操作的）的导电材料的伪影边缘，当实际上使用另一种类型的晶体管时。
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公开(公告)号：US07514755B2
公开(公告)日：2009-04-07
申请号：US10735841
申请日：2003-12-12
IPC分类号： H01L29/76
CPC分类号： H01L21/823892 , H01L27/02
摘要： A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed having a well of a first conductivity type under the gate region being disposed adjacent to active regions of a first conductivity type. The well forming an electrical path between the active regions regardless of any reasonable voltage applied to the integrated circuit structure.
摘要翻译： 用于伪装集成电路结构的技术和结构。 集成电路结构形成为具有第一导电类型的阱，栅极区域邻近第一导电类型的有源区设置。 该阱在有源区域之间形成电路径，而不管施加到集成电路结构的任何合理的电压。
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