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47 条记录 (耗时 0.026 秒)

    Charge-coupled device with focused ion beam fabrication
    1.
    发明授权
    Charge-coupled device with focused ion beam fabrication 失效
    具有聚焦离子束制造的电荷耦合器件

    公开(公告)号：US4967250A

    公开(公告)日：1990-10-30

    申请号：US426481

    申请日：1989-10-23

    申请人： William M. Clark, Jr. ,  Robert H. Walden ,  Mark W. Utlaut

    发明人： William M. Clark, Jr. ,  Robert H. Walden ,  Mark W. Utlaut

    IPC分类号： H01L29/10

    CPC分类号： H01L29/1062

    摘要： A charge-coupled device (CCD) is provided with a dopant implant gradient, lateral channel stops and blocking implants by means of a focused ion beam (FIB). The FIB is repeatedly scanned across each cell of the CCD as a succession of overlapping but discrete implant scans. The doping levels of the FIB implants accumulate to a stepwise approximation of a desired dopant density profile, the widths of the steps being no greater than about half the widths of the discrete FIB implants. With a FIB pixel of about 750-1,500 Angstroms, the widths of the steps are preferably about 250-500 Angstroms; the dimension of the cells in the dopant gradient direction can be made less than about 5 microns. The lateral channel stops and back blocking implants can be as narrow as single FIB pixel widths, thus freeing up more of the cell for charge carrying capacity.

    摘要翻译： 电荷耦合器件（CCD）具有掺杂剂注入梯度，侧向通道通过聚焦离子束（FIB）停止和阻塞植入物。 FIB被重复地扫描在CCD的每个单元上，作为一系列重叠但离散的植入物扫描。 FIB植入物的掺杂水平累积到期望掺杂剂密度分布的逐步近似，步长的宽度不大于离散FIB植入物的宽度的大约一半。 具有约750-1,500埃的FIB像素，步长的宽度优选为约250-500埃; 可以使掺杂剂梯度方向上的单元的尺寸小于约5微米。 横向通道停止，背部阻挡植入物可以与单个FIB像素宽度一样窄，从而释放出更多的电池用于充电容量。

    Ion evaporation source for tin
    2.
    发明授权
    Ion evaporation source for tin 失效
    锡离子蒸发源

    公开(公告)号：US5006715A

    公开(公告)日：1991-04-09

    申请号：US352440

    申请日：1989-05-16

    申请人： Peter B. Back ,  Mark W. Utlaut ,  William M. Clark, Jr.

    发明人： Peter B. Back ,  Mark W. Utlaut ,  William M. Clark, Jr.

    IPC分类号： H01J27/26

    CPC分类号： H01J27/26

    摘要： An ion evaporation source for tin ions is prepared by coating a source element with a wettability enhancing gallium coating, and then loading the source with tin. The tin may be the naturally occurring tin, but can be an enriched tin containing a higher concentration of Sn.sup.120. The source produces a beam having a high fraction of Sn.sup.+ and Sn.sup.++ ions, and a small amount of the ionized wettability coating material. All but the desired ions are readily separated from the beam.

    摘要翻译： 通过涂覆具有润湿性增强镓涂层的源元件，然后用锡负载源来制备用于锡离子的离子蒸发源。 锡可以是天然存在的锡，但可以是含有较高浓度Sn120的富集锡。 该源产生具有高分数的Sn +和Sn ++离子的束，以及少量的电离润湿性涂层材料。 除了所需的离子之外，所有离子都容易与光束分离。

    Programmable connection and isolation of active regions in an integrated circuit using ambiguous features to confuse a reverse engineer
    5.
    发明授权
    Programmable connection and isolation of active regions in an integrated circuit using ambiguous features to confuse a reverse engineer 失效
    使用模糊特征对集成电路中的有源区域进行可编程连接和隔离，从而使反向工程师混淆

    公开(公告)号：US08168487B2

    公开(公告)日：2012-05-01

    申请号：US11855005

    申请日：2007-09-13

    申请人： William M. Clark, Jr. ,  Lap Wai Chow ,  Gavin Harbison ,  Paul Ouyang

    发明人： William M. Clark, Jr. ,  Lap Wai Chow ,  Gavin Harbison ,  Paul Ouyang

    IPC分类号： H01L21/335

    CPC分类号： H01L27/0203 ,  H01L23/573 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A technique for and structures for camouflaging an integrated circuit structure and strengthen its resistance to reverse engineering. A plurality of transistors are formed in a semiconductor substrate, at least some of the transistors being of the type having sidewall spacers with LDD regions formed under the sidewall spacers. Transistors are programmably interconnected with ambiguous interconnection features, the ambiguous interconnection features each comprising a channel formed in the semiconductor substrate with preferably the same dopant density as the LDD regions, with selected ones of the channels being formed of a conductivity type supporting electrical communication between interconnected active regions and with other selected ones of the channels being formed of a conductivity type inhibiting electrical communication but ambiguously appearing to a reverse engineer as supporting electrical communication.

    摘要翻译： 用于伪装集成电路结构的技术和结构，并加强其对逆向工程的抵抗力。 在半导体衬底中形成多个晶体管，至少一些晶体管是具有侧壁间隔物的类型，其中LDD区形成在侧壁间隔物下。 晶体管可编程地与不明确的互连特征相互连接，这些不明确的互连特征各自包括形成在半导体衬底中的通道，其优选地与LDD区域具有相同的掺杂剂密度，其中选定的通道由导电类型形成，支持互连 有源区域和其它选择的通道由导电类型抑制电气通信形成，但是对于逆向工程师而言，这些通道似乎是支持电气通信。

    Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact
    7.
    发明授权
    Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact 失效
    永久性地使用采用双重多晶硅层CMOS工艺的埋入触点实现晶体管

    公开(公告)号：US06740942B2

    公开(公告)日：2004-05-25

    申请号：US09882892

    申请日：2001-06-15

    申请人： James P. Baukus ,  Lap-Wai Chow ,  William M. Clark, Jr.

    发明人： James P. Baukus ,  Lap-Wai Chow ,  William M. Clark, Jr.

    IPC分类号： H01L2976

    CPC分类号： H01L27/0203 ,  H01L21/76895 ,  H01L21/823462 ,  H01L23/576 ,  H01L27/0883 ,  H01L29/7834 ,  H01L2924/0002 ,  Y10S257/922 ,  H01L2924/00

    摘要： A permanently-ON MOS transistor comprises silicon source and drain regions of a first conductivity type in a silicon well region of a second conductivity type. A silicon contact region of the first conductivity types is buried in the well region, said contact region contacting said source region and said drain region. A first gate insulating layer is selectively placed over the silicon source and drain regions. A second gate insulating layer is selectively placed over the first gate insulating layer and over the silicon contact region. A polysilicon gate region is placed over the second gate insulating layer.

    摘要翻译： 永久导通MOS晶体管包括在第二导电类型的硅阱区域中的第一导电类型的硅源极和漏极区域。 所述第一导电类型的硅接触区域埋在所述阱区域中，所述接触区域接触所述源极区域和所述漏极区域。 选择性地将第一栅极绝缘层放置在硅源极和漏极区域上。 第二栅极绝缘层选择性地放置在第一栅极绝缘层上方和硅接触区域上。 多晶硅栅极区域放置在第二栅极绝缘层上。