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公开(公告)号：US20090315409A1
公开(公告)日：2009-12-24
申请号：US12362024
申请日：2009-01-29
IPC分类号： H02H3/40
CPC分类号： H01R13/665 , H01R13/6683 , H02H3/42 , Y10T307/832
摘要： A digital automatic monitoring and power breaking safety socket has a shell in which an electrical connection base is mounted for connecting to a power line and an external line plug inside. A power switch is connected in series between the electrical connection base and the power line. A digital power monitoring circuit is coupled to the power line detect the power status to control the power switch based on the power status. Further, a power line data communication circuit is mounted in the shell and connects to the digital power monitoring circuit to obtain and process the power status. The processed power status is loaded into the power line that connects to the electrical connection base. Therefore, in addition to automatic power breaking and supplying, a remote power management host is able to obtain the power status and remotely control the socket.
摘要翻译： 数字自动监测和断电安全插座具有壳体，其中安装有电连接基座用于连接到电力线和外部线路插头。 电源开关串联在电气连接基座和电源线之间。 数字电源监控电路耦合到电源线，根据电源状态检测电源状态，控制电源开关。 此外，电源线数据通信电路安装在外壳中并连接到数字电源监控电路以获得并处理电源状态。 处理后的电源状态被加载到连接到电气连接基座的电力线上。 因此，除了自动断电和供电之外，远程电源管理主机能够获得电源状态并远程控制插座。
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2.发明申请公开(公告)号：US20090024804A1
公开(公告)日：2009-01-22
申请号：US12207476
申请日：2008-09-09
IPC分类号： G06F12/10
CPC分类号： G06F13/1642
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.
摘要翻译： 描述了基于并行硬件的多线程处理器。 处理器包括协调系统功能的通用处理器和支持多个硬件线程的多个微启动器。 处理器还包括存储器控制系统，该存储器控制系统具有第一存储器控制器，该第一存储器控制器基于存储器引用是针对偶数存储体还是存储器的奇数存储器来分类存储器引用;以及第二存储器控制器，其基于存储器是否优化存储器引用 引用是读取引用或写入引用。
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公开(公告)号：US07107201B2
公开(公告)日：2006-09-12
申请号：US09941952
申请日：2001-08-29
CPC分类号： G06F17/5022
摘要： Simulating a logic design having combinatorial logic and state logic includes representing the combinatorial logic and the state logic using separate graphic elements, identifying clock domains for the combinatorial logic and the state logic using the separate graphic elements, generating computer code that simulates operation of portions of the logic design, the computer code being generated based on the clock domains, and associating the computer code with graphic elements that correspond to the portions of the logic design.
摘要翻译： 模拟具有组合逻辑和状态逻辑的逻辑设计包括使用分离的图形元素表示组合逻辑和状态逻辑，识别用于组合逻辑的时钟域和使用分离的图形元素的状态逻辑，生成计算机代码，其模拟部分的操作 逻辑设计，基于时钟域产生的计算机代码，以及将计算机代码与对应于逻辑设计的部分的图形元素相关联。
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公开(公告)号：US07093224B2
公开(公告)日：2006-08-15
申请号：US09941158
申请日：2001-08-28
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5022
摘要： A technique for designing a logic circuit includes specifying a model. The model including combinatorial blocks, state elements and graphical library elements. The technique maintains a data structure representative of the model, and generates an architectural model and an implementation model from the data structure. The data structure represents a descriptive net list of the model. The architectural model includes C++ code and the implementation model includes Verilog.
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公开(公告)号：US07073156B2
公开(公告)日：2006-07-04
申请号：US09941519
申请日：2001-08-29
CPC分类号： G06F17/5045
摘要： A circuit design parameter file is maintained for a circuit being designed by a circuit designer. This circuit design parameter file specifies a physical characteristic of the circuit. A design environment is monitored to detect the addition of a circuitry component to the circuit and a component design parameter file that specifies at least one design parameter for that added circuitry component is accessed. The circuit design parameter file is updated based on the design parameter(s) included in the component design parameter file. The circuit designer is provided with feedback concerning the physical characteristic of the circuit being designed.
摘要翻译： 为由电路设计者设计的电路维护电路设计参数文件。 该电路设计参数文件指定电路的物理特性。 监视设计环境以检测电路组件到电路的添加，并且访问指定所添加的电路组件的至少一个设计参数的组件设计参数文件。 电路设计参数文件根据组件设计参数文件中包含的设计参数进行更新。 电路设计人员提供有关正在设计的电路的物理特性的反馈。
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公开(公告)号：US06983350B1
公开(公告)日：2006-01-03
申请号：US09387109
申请日：1999-08-31
IPC分类号： G06F12/00
CPC分类号： G06F13/1642
摘要： A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.
摘要翻译： 描述了基于并行硬件的多线程处理器。 处理器包括协调系统功能的通用处理器和支持多个硬件线程的多个微启动器。 处理器还包括存储器控制系统，该存储器控制系统具有第一存储器控制器，该第一存储器控制器基于存储器引用是针对偶数存储体还是存储器的奇数存储器来分类存储器引用;以及第二存储器控制器，其基于存储器是否优化存储器引用 引用是读取引用或写入引用。
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7.发明授权Employing intelligent logical models to enable concise logic representations for clarity of design description and for rapid design capture 失效采用智能逻辑模型来实现简洁的逻辑表示，以便设计描述清晰，并能快速设计公开(公告)号：US06721925B2
公开(公告)日：2004-04-13
申请号：US10025193
申请日：2001-12-18
IPC分类号： G06F1750
CPC分类号： G06F17/5022 , G06F17/5045
摘要： Representing a logic device generally includes creating a model of a logic device, where the model represents a collection of variants of the logic device. A representation of the model may be used in a logic design and a particular variant of the logic device may be selected automatically based on connections made to the representation. Connection errors may be detected automatically and a first indication may be displayed automatically when the connection errors are detected. A second indication that differs from the first indication may be displayed automatically when the connection errors are corrected.
摘要翻译： 代表逻辑设备通常包括创建逻辑设备的模型，其中模型表示逻辑设备的变体的集合。 可以在逻辑设计中使用该模型的表示，并且可以基于对表示形成的连接来自动选择逻辑设备的特定变体。 可以自动检测连接错误，并且当检测到连接错误时可以自动显示第一指示。 当修正连接错误时，可以自动显示与第一指示不同的第二指示。
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8.发明授权
公开(公告)号：US5119483A
公开(公告)日：1992-06-02
申请号：US221944
申请日：1988-07-20
CPC分类号： G06F9/3867 , G06F9/26 , G06F9/30149 , G06F9/3863 , G06F12/10 , Y10S707/99939
摘要： To reduce the processing time required for correcting a fault, the instruction decorder segment and the first execution segment of a pipelined processor are provided with "state silos" that are operative during normal instruction execution to save a sufficient amount of state information to immediately restart the instruction decoder segment and the first execution segment by reloading the state information having been stored in the state silos. The state silos, for example, include a queue of registers clocked by a common clocking signal that is inhibited during correction of the fault. When the fault is corrected, multiplexers select the state information from the silos to be used by the respective pipeline segments. In a preferred embodiment, the instruction decoder segment decodes variable length macroinstructions into operand specifiers and operations to perform upon the specifiers. The first execution segment receives control information when a new operand specifier or operation is decoded, and otherwise holds the previously received control information. A microsequencer issues a series of microinstructions for each specifier or operation having been decoded, and also issues a series of microinstructions in a fault routine when a fault occurs. The microsequencer is also provided with a state silo so that the normal sequence of microinstruction execution is resumed when the fault is corrected.
摘要翻译： 为了减少纠正故障所需的处理时间，流水线处理器的指令解码段和第一执行段被提供有在正常指令执行期间操作的“状态仓”以保存足够量的状态信息以立即重启 指令解码器段和第一执行段，通过重新加载已经存储在状态列表中的状态信息。 例如，状态孤岛包括由校正故障期间被禁止的公共时钟信号计时的寄存器队列。 当故障被纠正时，多路复用器从相应流水线段使用的筒仓中选择状态信息。 在优选实施例中，指令解码器段将可变长度宏指令解码为操作数说明符和在指定符上执行的操作。 当新的操作数说明符或操作被解码时，第一执行段接收控制信息，否则保持先前接收到的控制信息。 微定序器为每个说明符或操作已经解码了一系列微指令，并且在出现故障时也会在故障程序中发出一系列微指令。 微定序器还设置有状态仓，使得当故障被校正时，微指令执行的正常序列被恢复。
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9.发明授权Non-contacting resistivity instrument with structurally related conductance and distance measuring transducers 失效具有结构相关电导和距离测量传感器的非接触电阻率仪器
公开(公告)号：US4302721A
公开(公告)日：1981-11-24
申请号：US39303
申请日：1979-05-15
CPC分类号： G01N27/023 , G01R31/2648 , G01R31/265 , G01R31/2831 , G01S15/32 , Y10S414/135
摘要： An instrument for computing resistivity based upon measurements of thickness and conductance. A conductance transducer is a solenoid in an annular ferrite cup connected to a tank circuit for an eddy current measurement of conductance. Within the center of the annular ferrite cup concentric acoustic wave sending and receiving channels are disposed for making an acoustic pressure wave measurement which is used for a thickness measurement using two gauge heads, spaced on opposite sides of an article to be measured. Each gauge head contains identical conductance and thickness transducers. The thickness measurement is divided by the conductance measurement to derive resistivity.
摘要翻译： 基于厚度和电导测量计算电阻率的仪器。 电导传感器是连接到用于电导涡流测量的电路的环形铁氧体杯中的螺线管。 在环形铁氧体杯的中心内，设置同心声波发送和接收通道，用于进行声压测量，其用于使用两个测量头进行厚度测量，间隔在待测物品的相对两侧。 每个测量头包含相同的电导和厚度换能器。 厚度测量除以电导测量以导出电阻率。
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公开(公告)号：US10032431B2
公开(公告)日：2018-07-24
申请号：US14768141
申请日：2014-03-13
申请人： Myles Wilde , Matthew J. Adiletta , William R. Wheeler , Michael F. Fallon , Thomas M. Garrison , Aaron Gorius , Chengda Yang
发明人： Myles Wilde , Matthew J. Adiletta , William R. Wheeler , Michael F. Fallon , Thomas M. Garrison , Aaron Gorius , Chengda Yang
IPC分类号： G09G5/00 , H04L29/06 , G06F13/38 , H04N19/423 , H04N19/44 , G06T1/60 , H04N5/38 , H04W4/18 , H04W4/21 , H04W4/80 , H04W76/14
摘要： Mobile computing device technology and systems and methods using the same are described herein. In particular, mobile computing devices that may serve as a processing component of a disaggregated computing system described, non-integral screens that may be paired with the mobile computing devices, and systems and methods using such devices and screens are described. In some embodiments, the mobile computing device technology includes a mobile computing device that lacks an integral screen, but which is capable of throwing at least video information to a non-integral target screen, e.g., via a paired connection established over a wired or wireless communication interface.
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