公开(公告)号：US20070249115A1

公开(公告)日：2007-10-25

申请号：US11408752

申请日：2006-04-21

申请人： Wing Luk ,  Jin Cai

发明人： Wing Luk ,  Jin Cai

IPC分类号： H01L21/8244 ,  H01L29/94

CPC分类号： G11C11/4097 ,  G11C7/18 ,  G11C8/16 ,  G11C11/405 ,  H01L21/28079 ,  H01L21/84 ,  H01L27/10873 ,  H01L29/495

摘要： A dynamic random access memory cell is disclosed that comprises a capacitive storage device and a write access transistor. The write access transistor is operatively coupled to the capacitive storage device and has a gate stack that comprises a high-K dielectric, wherein the high-K dielectric has a dielectric constant greater than a dielectric constant of silicon dioxide. Also disclosed are a memory array using the cells, a computing apparatus using the memory array, a method of storing data, and a method of manufacturing.

摘要翻译： 公开了一种动态随机存取存储器单元，其包括电容存储器件和写入存取晶体管。 写入存取晶体管可操作地耦合到电容存储器件，并且具有包括高K电介质的栅极堆叠，其中高K电介质具有大于二氧化硅介电常数的介电常数。 还公开了使用这些单元的存储器阵列，使用存储器阵列的计算装置，存储数据的方法和制造方法。

公开(公告)号：US20070041373A1

公开(公告)日：2007-02-22

申请号：US11206085

申请日：2005-08-18

申请人： Kar-Wing Lor ,  Wing Luk ,  Kwan Shum

发明人： Kar-Wing Lor ,  Wing Luk ,  Kwan Shum

IPC分类号： H04L12/66

CPC分类号： H04L45/00 ,  H04L29/06027 ,  H04L47/20 ,  H04L47/2416 ,  H04L47/32 ,  H04L65/1069 ,  H04M3/42314 ,  H04M7/006

摘要： A switching apparatus for switching packetized voice traffic between a plurality of communication devices, the switching apparatus comprises a multi-layer switch, a plurality of communication ports, control means and ingress processing means, said packetized voice traffic comprises call control packets and medium packets which are exchanged between the communication devices via said communication ports, wherein medium packet traffic from a first communication device to a second communication device is split into a first call segment and a second call segment, the first call segment originates from said first communication devices and terminates at said switching apparatus, the second call segment originates from said switching apparatus and terminates at said second communication device, each medium packet from said first communication device is processed by said ingress processing means of said switching apparatus before onward transmission to said second communication device.

摘要翻译： 一种用于在多个通信设备之间切换分组语音业务的交换设备，所述交换设备包括多层交换机，多个通信端口，控制装置和入口处理装置，所述分组语音业务包括呼叫控制分组和媒体分组， 经由所述通信端口在通信设备之间交换，其中从第一通信设备到第二通信设备的中分组业务被分为第一呼叫段和第二呼叫段，第一呼叫段来自所述第一通信设备并终止 在所述交换装置中，所述第二呼叫段起始于所述交换设备，并终止于所述第二通信设备，所述第一通信设备的每个媒体分组由所述交换设备的所述入口处理装置在向前发送到所述第二通信设备之前进行处理。

公开(公告)号：US20060039179A1

公开(公告)日：2006-02-23

申请号：US11248863

申请日：2005-10-12

申请人： Wing Luk ,  Robert Dennard ,  Stephen Kosonocky

发明人： Wing Luk ,  Robert Dennard ,  Stephen Kosonocky

IPC分类号： G11C11/24

CPC分类号： G11C5/063 ,  G11C11/406 ,  G11C11/4074 ,  G11C2207/104

摘要： An integrated circuit, such as a memory macro, includes multiple power rails supporting first and second voltage differentials, with the second voltage differential being smaller than the first voltage differential. Signal lines in the integrated circuit are driven with the small voltage swing, which is generated by small swing circuits. The integrated circuit further includes regeneration circuits, which are receiving small voltage swing inputs and are outputting first, or full voltage swings. The application of the small voltage swing to the signal lines saves power in the integrated circuit. A wide bandwidth, full-wordline I/O, memory integrated circuit has simultaneously operable connection paths between essentially all the memory cells that are attached to the same wordline and the corresponding I/O terminals, and it has a single ended data-line structure.

摘要翻译： 诸如存储器宏的集成电路包括支持第一和第二电压差的多个电源轨，第二电压差小于第一电压差。 集成电路中的信号线由小的摆动电路产生的小电压摆动驱动。 集成电路还包括正在接收小电压摆幅输入并且正在输出第一或全电压摆幅的再生电路。 将小电压摆幅应用于信号线节省了集成电路中的功率。 宽带宽全字I / O存储器集成电路具有在连接到相同字线和对应的I / O端子的基本上所有存储单元之间的同时可操作的连接路径，并且具有单端数据线结构 。

公开(公告)号：US20070044141A1

公开(公告)日：2007-02-22

申请号：US11206083

申请日：2005-08-18

申请人： Kar-Wing Lor ,  Yat Cheung ,  Wing Luk ,  Kwan Shum

发明人： Kar-Wing Lor ,  Yat Cheung ,  Wing Luk ,  Kwan Shum

IPC分类号： H04L9/32

CPC分类号： H04L63/162 ,  H04L29/12839 ,  H04L61/6022 ,  H04L63/0236 ,  H04L63/08 ,  H04L63/0876 ,  H04M7/006 ,  H04M7/0078

摘要： An admission scheme for a communication network comprising the step of:—a) acquiring and storing the MAC address of a device on admitting the device to the communication network, b) checking the source MAC address of a data packet before said data packet is admitted into the communication network, and c) admitting a data packet into the communication network only if the MAC address is registered with the communication network.

摘要翻译： 一种用于通信网络的接纳方案，包括以下步骤：a）获取并存储将设备接纳到通信网络的设备的MAC地址; b）在所述数据分组被允许之前检查数据分组的源MAC地址 进入通信网络，以及c）仅当所述MAC地址被注册到所述通信网络时才允许将数据分组传入所述通信网络。

公开(公告)号：US20050052897A1

公开(公告)日：2005-03-10

申请号：US10656596

申请日：2003-09-05

申请人： Wing Luk ,  Robert Dennard

发明人： Wing Luk ,  Robert Dennard

IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C11/24 ,  G11C11/4091

CPC分类号： G11C7/1039 ,  G11C7/067 ,  G11C11/4091 ,  G11C2207/104

摘要： A DRAM is disclosed which includes a single ended bitline structure, a single ended global bitline structure, primary sense amplifiers with data storage and data write-back capability and with capability to decouple from the global bitlines, a full-wordline I/O structure where essentially all memory cell that belong to the same wordline are being operated on, and a pipelined architecture. The DRAM further includes a small voltage swing design. The primary sense amplifiers can include more than one amplification stages. Such a DRAM is suitable for applications in conjunction with processors as an embedded DRAM.

摘要翻译： 公开了一种DRAM，其包括单端位线结构，单端全局位线结构，具有数据存储和数据回写能力的初级读出放大器，以及具有与全局位线分离的能力的全字I / O结构，其中 基本上所有属于相同字线的所有存储器单元正在被操作，以及流水线架构。 DRAM还包括小电压摆幅设计。 主感测放大器可以包括多于一个的放大级。 这样的DRAM适用于作为嵌入式DRAM的处理器的应用。

公开(公告)号：US20060198181A1

公开(公告)日：2006-09-07

申请号：US11067797

申请日：2005-02-28

申请人： Wing Luk ,  Leland Chang

发明人： Wing Luk ,  Leland Chang

IPC分类号： G11C11/00

CPC分类号： G11C11/413

摘要： A new type of static RAM cell is disclosed that is based on a gated diode and its voltage amplification characteristic. The cell combines the advantages of a static RAM, in which data refresh is not needed, and those of gated diode cells, which are scalable to low voltages, have high signal to noise ratio, high signal margin, and tolerance to process variations, to form a single high performance static memory cell. This new cell has independent read and write paths, which allow for separate optimization of the read (R) and write (W) events, and enable dual-port R/W operation. Furthermore, storage node disturbance during the read and write operations are eliminated, which greatly improves cell stability and scalability for future technologies.

摘要翻译： 公开了一种基于门控二极管及其电压放大特性的新型静态RAM单元。 该单元结合了不需要数据刷新的静态RAM和可扩展到低电压的门控二极管单元的优点具有高信噪比，高信号余量和对工艺变化的公差， 形成单个高性能静态存储单元。 这个新单元格具有独立的读写路径，允许单独优化读（R）和写（W）事件，并启用双端口R / W操作。 此外，消除了在读取和写入操作期间的存储节点干扰，这大大地改善了用于未来技术的小区稳定性和可扩展性。

公开(公告)号：US20060050581A1

公开(公告)日：2006-03-09

申请号：US10933706

申请日：2004-09-03

申请人： Wing Luk ,  Leland Chang ,  Robert Dennard ,  Robert Montoye

发明人： Wing Luk ,  Leland Chang ,  Robert Dennard ,  Robert Montoye

IPC分类号： G11C7/00

CPC分类号： G11C7/065 ,  G11C7/06 ,  H03F1/56 ,  H03F3/10 ,  H03F3/347 ,  H03F2200/183

摘要： A sense amplifier circuit comprises (1) an isolation device comprising a control terminal and first and second terminals, the first terminal of the isolation device coupled to a signal line, (2) a gated diode comprising first and second terminals, the first terminal of the gated diode coupled to the second terminal of the isolation device, and the second terminal of the gated diode coupled to a set line; and (3) control circuitry coupled to the control terminal of the isolation device and adapted to control voltage on the control terminal of the isolation device in order to enable and disable the isolation device. A latch circuit further comprises a precharge device comprising a control terminal and first and second terminals, the first terminal of the precharge device coupled to a power supply voltage, and the second terminal of the precharge device coupled to the first terminal of the isolation device.

公开(公告)号：US20050145895A1

公开(公告)日：2005-07-07

申请号：US10751714

申请日：2004-01-05

申请人： Wing Luk ,  Robert Dennard

发明人： Wing Luk ,  Robert Dennard

IPC分类号： G11C7/06 ,  H01L27/08 ,  H01L29/739 ,  H03F1/56 ,  H01L21/336 ,  H01L29/94

CPC分类号： H03F1/56 ,  G11C7/06 ,  H01L27/0811 ,  H01L29/7391 ,  H03F2200/183

摘要： A circuit comprises a control line and a two terminal semiconductor device having first and second terminals. The first terminal is coupled to a signal line, and the second terminal is coupled to the control line. The two terminal semiconductor device is adapted to have a capacitance when a voltage on the first terminal relative to the second terminal is above a threshold voltage and to have a smaller capacitance when a voltage on the first terminal relative to the second terminal is below the threshold voltage. The control line is coupled to a control signal and the signal line is coupled to a signal and is output of the circuit. A signal is placed on the signal line and voltage on the control line is modified (e.g., raised in the case of n-type devices, or lowered for a p-type devices). When the signal falls below the threshold voltage, the two terminal semiconductor device acts as a very small capacitor and the output of the circuit will be a small value. When the signal is above the threshold voltage, the two terminal semiconductor device acts as a large capacitor and the output of the circuit will be influenced by both the value of the signal and the value of the modified voltage on the control line and therefore the signal will be amplified.

摘要翻译： 电路包括控制线和具有第一和第二端子的两端子半导体器件。 第一端子耦合到信号线，并且第二端子耦合到控制线。 当第一端子上相对于第二端子的电压高于阈值电压时，两端子半导体器件适于具有电容，并且当第一端子上相对于第二端子的电压低于阈值时具有较小的电容 电压。 控制线耦合到控制信号，并且信号线耦合到信号并且是电路的输出。 将信号放置在信号线上，并且控制线上的电压被修改（例如在n型器件的情况下升高，或者对于p型器件降低）。 当信号低于阈值电压时，两端子半导体器件作为一个非常小的电容器，并且电路的输出将是一个小的值。 当信号高于阈值电压时，两端子半导体器件用作大电容器，电路的输出将受到信号值和控制线上修改电压值的影响，因此信号 将被放大。

公开(公告)号：US20050073871A1

公开(公告)日：2005-04-07

申请号：US10680348

申请日：2003-10-07

申请人： Wing Luk ,  Robert Dennard

发明人： Wing Luk ,  Robert Dennard

IPC分类号： G11C11/405 ,  H01L27/108 ,  G11C11/24

CPC分类号： H01L27/108 ,  G11C11/405

摘要： A random access memory (RAM) circuit is coupled to a write control line, a read control line, and one or more bitlines, and includes a write switch having a control terminal and first and second terminals. The first terminal of the write switch is coupled to the one or more bitlines, and the control terminal of the write switch is coupled to the write control line. The circuit includes a charge-storage device having first and second terminals, wherein a first terminal of the charge-storage device is coupled to the second terminal of the write switch and a second terminal of the charge-storage device is coupled to the read control line. The circuit includes a read switch having a control terminal and first and second terminals. The control terminal of the read switch is coupled to the first terminal of the charge-storage device and is coupled to the second terminal of the write switch. The first terminal of the read switch is coupled to the one or more bitlines, and the second terminal of the read switch coupled to ground. The circuit may be implemented through a number of disclosed semiconductor memory devices.

摘要翻译： 随机存取存储器（RAM）电路耦合到写入控制线，读取控制线和一个或多个位线，并且包括具有控制端子和第一和第二端子的写入开关。 写开关的第一端耦合到一个或多个位线，并且写开关的控制端耦合到写控制线。 该电路包括具有第一和第二端子的电荷存储装置，其中电荷存储装置的第一端子耦合到写入开关的第二端子，并且电荷存储装置的第二端子耦合到读取控制 线。 电路包括具有控制端子和第一和第二端子的读取开关。 读开关的控制端耦合到电荷存储装置的第一端并耦合到写开关的第二端。 读开关的第一端耦合到一个或多个位线，并且读开关的第二端耦合到地。 电路可以通过许多公开的半导体存储器件实现。

公开(公告)号：US20060255850A1

公开(公告)日：2006-11-16

申请号：US11491701

申请日：2006-07-24

申请人： Wing Luk ,  Leland Chang ,  Robert Dennard ,  Robert Montoye

发明人： Wing Luk ,  Leland Chang ,  Robert Dennard ,  Robert Montoye

IPC分类号： H03K3/356

CPC分类号： G11C7/065 ,  G11C7/06 ,  H03F1/56 ,  H03F3/10 ,  H03F3/347 ,  H03F2200/183

摘要： A sense amplifier circuit comprises (1) an isolation device comprising a control terminal and first and second terminals, the first terminal of the isolation device coupled to a signal line, (2) a gated diode comprising first and second terminals, the first terminal of the gated diode coupled to the second terminal of the isolation device, and the second terminal of the gated diode coupled to a set line; and (3) control circuitry coupled to the control terminal of the isolation device and adapted to control voltage on the control terminal of the isolation device in order to enable and disable the isolation device. A latch circuit further comprises a precharge device comprising a control terminal and first and second terminals, the first terminal of the precharge device coupled to a power supply voltage, and the second terminal of the precharge device coupled to the first terminal of the isolation device.

摘要翻译： 读出放大器电路包括（1）隔离装置，其包括控制端子和第一和第二端子，隔离装置的第一端子耦合到信号线，（2）门控二极管，包括第一和第二端子，第一端子 所述门控二极管耦合到隔离装置的第二端子，并且门控二极管的第二端子耦合到设定线路; 和（3）耦合到隔离装置的控制端子并且适于控制隔离装置的控制端子上的电压的控制电路，以便启用和禁用隔离装置。 闩锁电路还包括预充电装置，其包括控制端子和第一和第二端子，预充电装置的第一端子耦合到电源电压，并且预充电装置的第二端子耦合到隔离装置的第一端子。