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    Semiconductor device test structures and methods
    1.
    发明授权
    Semiconductor device test structures and methods 有权
    半导体器件测试结构及方法

    公开(公告)号：US07858406B2

    公开(公告)日：2010-12-28

    申请号：US11702975

    申请日：2007-02-06

    申请人： Wolfgang Walter ,  Klaus Koller

    发明人： Wolfgang Walter ,  Klaus Koller

    IPC分类号： G01R31/26

    CPC分类号： G01R31/2607 ,  G01R31/2858 ,  H01L22/34 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Semiconductor device test structures and methods are disclosed. In a preferred embodiment, a test structure includes a feed line disposed in a first conductive material layer, and a stress line disposed in the first conductive material layer proximate the feed line yet spaced apart from the feed line. The stress line is coupled to the feed line by a conductive feature disposed in at least one second conductive material layer proximate the first conductive material layer.

    摘要翻译： 公开了半导体器件测试结构和方法。 在优选实施例中，测试结构包括设置在第一导电材料层中的馈电线，以及设置在第一导电材料层中的紧靠馈电线但与馈电线间隔开的应力线。 应力线通过布置在靠近第一导电材料层的至少一个第二导电材料层中的导电特征耦合到馈电线。

    Semiconductor device test structures and methods
    2.
    发明申请
    Semiconductor device test structures and methods 有权
    半导体器件测试结构及方法

    公开(公告)号：US20080185584A1

    公开(公告)日：2008-08-07

    申请号：US11702975

    申请日：2007-02-06

    申请人： Wolfgang Walter ,  Klaus Koller

    发明人： Wolfgang Walter ,  Klaus Koller

    IPC分类号： H01L23/58 ,  H01L21/4763 ,  H01L21/66

    CPC分类号： G01R31/2607 ,  G01R31/2858 ,  H01L22/34 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Semiconductor device test structures and methods are disclosed. In a preferred embodiment, a test structure includes a feed line disposed in a first conductive material layer, and a stress line disposed in the first conductive material layer proximate the feed line yet spaced apart from the feed line. The stress line is coupled to the feed line by a conductive feature disposed in at least one second conductive material layer proximate the first conductive material layer.

    摘要翻译： 公开了半导体器件测试结构和方法。 在优选实施例中，测试结构包括设置在第一导电材料层中的馈电线，以及设置在第一导电材料层中的紧靠馈电线但与馈电线间隔开的应力线。 应力线通过布置在靠近第一导电材料层的至少一个第二导电材料层中的导电特征耦合到馈电线。

    Semiconductor device test structures and methods
    3.
    发明授权
    Semiconductor device test structures and methods 有权
    半导体器件测试结构和方法

    公开(公告)号：US08633482B2

    公开(公告)日：2014-01-21

    申请号：US12949088

    申请日：2010-11-18

    申请人： Wolfgang Walter ,  Klaus Koller

    发明人： Wolfgang Walter ,  Klaus Koller

    IPC分类号： H01L23/52

    CPC分类号： G01R31/2607 ,  G01R31/2858 ,  H01L22/34 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Semiconductor device test structures and methods are disclosed. In a preferred embodiment, a test structure includes a feed line disposed in a first conductive material layer, and a stress line disposed in the first conductive material layer proximate the feed line yet spaced apart from the feed line. The stress line is coupled to the feed line by a conductive feature disposed in at least one second conductive material layer proximate the first conductive material layer.

    摘要翻译： 公开了半导体器件测试结构和方法。 在优选实施例中，测试结构包括设置在第一导电材料层中的馈电线，以及设置在第一导电材料层中的紧靠馈电线但与馈电线间隔开的应力线。 应力线通过布置在靠近第一导电材料层的至少一个第二导电材料层中的导电特征耦合到馈电线。

    Semiconductor Device Test Structures and Methods
    4.
    发明申请
    Semiconductor Device Test Structures and Methods 有权
    半导体器件测试结构与方法

    公开(公告)号：US20110062442A1

    公开(公告)日：2011-03-17

    申请号：US12949088

    申请日：2010-11-18

    申请人： Wolfgang Walter ,  Klaus Koller

    发明人： Wolfgang Walter ,  Klaus Koller

    IPC分类号： H01L23/48 ,  H01L21/66

    CPC分类号： G01R31/2607 ,  G01R31/2858 ,  H01L22/34 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Semiconductor device test structures and methods are disclosed. In a preferred embodiment, a test structure includes a feed line disposed in a first conductive material layer, and a stress line disposed in the first conductive material layer proximate the feed line yet spaced apart from the feed line. The stress line is coupled to the feed line by a conductive feature disposed in at least one second conductive material layer proximate the first conductive material layer.

    摘要翻译： 公开了半导体器件测试结构和方法。 在优选实施例中，测试结构包括设置在第一导电材料层中的馈电线，以及设置在第一导电材料层中的紧靠馈电线但与馈电线间隔开的应力线。 应力线通过布置在靠近第一导电材料层的至少一个第二导电材料层中的导电特征耦合到馈电线。

    Integrated semiconductor product with metal-insulator-metal capacitor
    6.
    发明申请
    Integrated semiconductor product with metal-insulator-metal capacitor 有权
    集成半导体产品与金属 - 绝缘体 - 金属电容器

    公开(公告)号：US20050012223A1

    公开(公告)日：2005-01-20

    申请号：US10865463

    申请日：2004-06-10

    申请人： Klaus Koller ,  Heinrich Korner ,  Michael Schrenk

    发明人： Klaus Koller ,  Heinrich Korner ,  Michael Schrenk

    IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L29/76 ,  H01L21/4763

    CPC分类号： H01L28/75 ,  H01L21/76838 ,  H01L28/55

    摘要： To fabricate an integrated semiconductor product with integrated metal-insulator-metal capacitor, first of all a dielectric auxiliary layer (6) is deposited on a first electrode (2, 3, 5). This auxiliary layer (6) is then opened up (15) via the first electrode. Then, a dielectric layer (7) is produced, and the metal track stack (8, 9, 10) for the second electrode is then applied to the dielectric layer (6). This is followed by the patterning of the metal-insulator-metal capacitor using known etching processes. This makes it possible to produce dielectric capacitor layers of any desired thickness using materials which can be selected as desired. In particular, this has the advantage that via etches can be carried out significantly more easily than in the prior art, since it is not necessary to etch through the residual dielectric capacitor layer above the metal tracks.

    摘要翻译： 为了制造具有集成金属 - 绝缘体 - 金属电容器的集成半导体产品，首先将介电辅助层（6）沉积在第一电极（2,3,5）上。 然后，该辅助层（6）经由第一电极打开（15）。 然后，制造电介质层（7），然后将用于第二电极的金属轨道堆叠（8,9,10）施加到电介质层（6）。 然后使用已知的蚀刻工艺对金属 - 绝缘体 - 金属电容器进行图案化。 这使得可以使用可以根据需要选择的材料来制造任何所需厚度的介电电容器层。 特别地，这具有以下优点：通过蚀刻可以比现有技术更容易地进行蚀刻，因为不需要通过金属轨道上方的残留介电电容器层进行蚀刻。

    Integrated semiconductor product with metal-insulator-metal capacitor
    8.
    发明授权
    Integrated semiconductor product with metal-insulator-metal capacitor 有权
    集成半导体产品与金属 - 绝缘体 - 金属电容器

    公开(公告)号：US07233053B2

    公开(公告)日：2007-06-19

    申请号：US10865463

    申请日：2004-06-10

    申请人： Klaus Koller ,  Heinrich Körner ,  Michael Schrenk

    发明人： Klaus Koller ,  Heinrich Körner ,  Michael Schrenk

    IPC分类号： H01L29/00 ,  H01L21/00

    CPC分类号： H01L28/75 ,  H01L21/76838 ,  H01L28/55

    摘要： To fabricate an integrated semiconductor product with integrated metal-insulator-metal capacitor, first of all a dielectric auxiliary layer (6) is deposited on a first electrode (2, 3, 5). This auxiliary layer (6) is then opened up (15) via the first electrode. Then, a dielectric layer (7) is produced, and the metal track stack (8, 9, 10) for the second electrode is then applied to the dielectric layer (6). This is followed by the patterning of the metal-insulator-metal capacitor using known etching processes. This makes it possible to produce dielectric capacitor layers of any desired thickness using materials which can be selected as desired. In particular, this has the advantage that via etches can be carried out significantly more easily than in the prior art, since it is not necessary to etch through the residual dielectric capacitor layer above the metal tracks.

    摘要翻译： 为了制造具有集成金属 - 绝缘体 - 金属电容器的集成半导体产品，首先将介电辅助层（6）沉积在第一电极（2,3,5）上。 然后，该辅助层（6）经由第一电极打开（15）。 然后，制造电介质层（7），然后将用于第二电极的金属轨道堆叠（8,9,10）施加到电介质层（6）。 然后使用已知的蚀刻工艺对金属 - 绝缘体 - 金属电容器进行图案化。 这使得可以使用可以根据需要选择的材料来制造任何所需厚度的介电电容器层。 特别地，这具有以下优点：通过蚀刻可以比现有技术更容易地进行蚀刻，因为不需要通过金属轨道上方的残余介电电容器层进行蚀刻。