公开(公告)号：US12142674B2

公开(公告)日：2024-11-12

申请号：US17859425

申请日：2022-07-07

Applicant: WOLFSPEED, INC.

Inventor： Saptharishi Sriram

IPC: H01L29/778 ,  H01L21/265 ,  H01L21/322 ,  H01L29/16 ,  H01L29/66 ,  H01L29/20

Abstract: A high-electron mobility transistor includes a substrate layer, a first buffer layer provided on the substrate layer, a barrier layer provided on the first buffer layer, a source provided on the barrier layer, a drain provided on the barrier layer, and a gate provided on the barrier layer. The transistor further includes a p-type material layer having a length parallel to a surface of the substrate layer over which the first buffer layer is provided, the length of the p-type material layer being less than an entire length of the substrate layer. The p-type material layer is provided in one of the following: the substrate layer, or the first buffer layer. A process of making the high-electron mobility transistor is disclosed as well.

公开(公告)号：US20230197841A1

公开(公告)日：2023-06-22

申请号：US17552555

申请日：2021-12-16

Applicant: WOLFSPEED, INC.

Inventor： Saptharishi Sriram

IPC: H01L29/778 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/0638 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/66462

Abstract: An apparatus includes a substrate; a group III-Nitride buffer layer on the substrate; a group III-Nitride barrier layer on the group III-Nitride buffer layer, the group III-Nitride barrier layer may include a higher bandgap than a bandgap of the group III-Nitride buffer layer; a source electrically coupled to the group III-Nitride barrier layer; a gate electrically coupled to the group III-Nitride barrier layer; a drain electrically coupled to the group III-Nitride barrier layer; and a conductive metallic region being at least one of the following: in the substrate or on the substrate below said group III-Nitride barrier layer. Additionally, the conductive metallic region is structured and arranged to extend a limited length parallel to said group III-Nitride barrier layer.

公开(公告)号：US11658234B2

公开(公告)日：2023-05-23

申请号：US17325576

申请日：2021-05-20

Applicant: Wolfspeed, Inc.

Inventor： Kyle Bothe ,  Terry Alcorn ,  Dan Namishia ,  Jia Guo ,  Matt King ,  Saptharishi Sriram ,  Jeremy Fisher ,  Fabian Radulescu ,  Scott Sheppard ,  Yueying Liu

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L29/7786 ,  H01L29/402 ,  H01L29/66462

Abstract: A transistor device includes a semiconductor epitaxial layer structure including a channel layer and a barrier layer on the channel layer, a source contact and a drain contact on the barrier layer, an insulating layer on the semiconductor layer between the source contact and the drain contact, and a gate contact on the insulating layer. The gate contact includes a central portion that extends through the insulating layer and contacts the barrier layer and a drain side wing that extends laterally from the central portion of the gate toward the drain contact by a distance ΓD. The drain side wing of the gate contact is spaced apart from the barrier layer by a distance d1 that is equal to a thickness of the insulating layer. The distance ΓD is less than about 0.3 μm, and the distance d1 is less than about 80 nm.

公开(公告)号：US20220376105A1

公开(公告)日：2022-11-24

申请号：US17325610

申请日：2021-05-20

Applicant: Wolfspeed, Inc.

Inventor： Jia Guo ,  Saptharishi Sriram ,  Scott Sheppard

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/40 ,  H01L21/76 ,  H01L21/765 ,  H01L29/66

Abstract: A transistor device according to some embodiments includes a channel layer, a barrier layer on the channel layer, and source and drain contacts on the barrier layer, and a gate contact on the barrier layer between the source and drain contacts. The channel layer includes a sub-layer having an increased doping concentration level relative to a remaining portion of the channel layer. The presence of the sub-layer may reduce drain lag without substantially increasing gate lag.

公开(公告)号：US11476359B2

公开(公告)日：2022-10-18

申请号：US16356234

申请日：2019-03-18

Applicant: WOLFSPEED, INC.

Inventor： Jia Guo ,  Scott Sheppard ,  Saptharishi Sriram

IPC: H01L31/072 ,  H01L29/778 ,  H01L29/06 ,  H01L29/66

Abstract: A device includes a substrate; a buffer layer on the substrate; a barrier layer on the buffer layer, a source electrically coupled to the barrier layer; a gate electrically coupled to the barrier layer; and a drain electrically coupled to the barrier layer. The device further includes an electron concentration reduction structure arranged with at least one of the following: in the barrier layer and on the barrier layer. The electron concentration reduction structure is configured to at least one of the following: reduce electron concentration around the gate, reduce electron concentration around an edge of the gate, reduce electron concentration, increase power gain, increase efficiency, decouple the gate from the drain, decouple the gate from the source, and reduce capacitance.

公开(公告)号：US11244831B2

公开(公告)日：2022-02-08

申请号：US16502771

申请日：2019-07-03

Applicant: Wolfspeed, Inc.

Inventor： Saptharishi Sriram ,  Yueying Liu

IPC: H01L21/266 ,  H01L29/778 ,  H01L29/20 ,  H01L29/08 ,  H01L21/265 ,  H01L29/417 ,  H01L29/423

Abstract: A transistor device is provided. The transistor device includes a substrate, a channel layer on the substrate, the channel layer including a GaN material, a barrier layer that is on the channel layer and that includes an AlGaN material, a drain electrode that is on the barrier layer in a drain region of the device, a source ohmic structure that is at least partially recessed into the barrier layer in a source region of the device, a source electrode that is on the source ohmic structure and a gate contact that is on the barrier layer and that is in a gate region of the device that is between the drain region and the source region.