公开(公告)号：US20090227116A1

公开(公告)日：2009-09-10

申请号：US12347289

申请日：2008-12-31

申请人： Moon Sig Joo ,  Heung Jae Cho ,  Yong Soo Kim ,  Won Joon Choi ,  Sung Jin Whang

发明人： Moon Sig Joo ,  Heung Jae Cho ,  Yong Soo Kim ,  Won Joon Choi ,  Sung Jin Whang

IPC分类号： H01L21/336

CPC分类号： H01L21/28282 ,  H01L29/513 ,  H01L29/792

摘要： A method for manufacturing a non-volatile memory device having a charge trap layer comprises in one embodiment: forming a first dielectric layer over a semiconductor substrate; forming a second dielectric layer having a higher dielectric constant than that of the first dielectric layer over the first dielectric layer; forming a nitride buffer layer for preventing an interfacial reaction over the second dielectric layer; forming a third dielectric layer by supplying a radical oxidation source onto the nitride buffer layer to oxidize the nitride buffer layer, thereby forming a tunneling layer comprising the first, second, and third dielectric layers; and forming a charge trap layer, a shielding layer, and a control gate electrode layer over the tunneling layer.

摘要翻译： 制造具有电荷陷阱层的非易失性存储器件的方法包括在一个实施例中：在半导体衬底上形成第一介电层; 在所述第一介电层上形成具有比所述第一介电层的介电常数更高的介电常数的第二电介质层; 形成用于防止所述第二介电层上的界面反应的氮化物缓冲层; 通过向所述氮化物缓冲层上提供自由基氧化源以氧化所述氮化物缓冲层而形成第三电介质层，从而形成包括所述第一，第二和第三电介质层的隧道层; 并在隧道层上形成电荷陷阱层，屏蔽层和控制栅极电极层。

公开(公告)号：US07736975B2

公开(公告)日：2010-06-15

申请号：US12347289

申请日：2008-12-31

申请人： Won Joon Choi ,  Moon Sig Joo ,  Heung Jae Cho ,  Yong Soo Kim ,  Sung Jin Whang

发明人： Won Joon Choi ,  Moon Sig Joo ,  Heung Jae Cho ,  Yong Soo Kim ,  Sung Jin Whang

IPC分类号： H01L21/336

CPC分类号： H01L21/28282 ,  H01L29/513 ,  H01L29/792

摘要： A method for manufacturing a non-volatile memory device having a charge trap layer comprises in one embodiment: forming a first dielectric layer over a semiconductor substrate; forming a second dielectric layer having a higher dielectric constant than that of the first dielectric layer over the first dielectric layer; forming a nitride buffer layer for preventing an interfacial reaction over the second dielectric layer; forming a third dielectric layer by supplying a radical oxidation source onto the nitride buffer layer to oxidize the nitride buffer layer, thereby forming a tunneling layer comprising the first, second, and third dielectric layers; and forming a charge trap layer, a shielding layer, and a control gate electrode layer over the tunneling layer.

摘要翻译： 制造具有电荷陷阱层的非易失性存储器件的方法包括在一个实施例中：在半导体衬底上形成第一介电层; 在所述第一介电层上形成具有比所述第一介电层的介电常数更高的介电常数的第二电介质层; 形成用于防止所述第二介电层上的界面反应的氮化物缓冲层; 通过向所述氮化物缓冲层上提供自由基氧化源以氧化所述氮化物缓冲层而形成第三电介质层，从而形成包括所述第一，第二和第三电介质层的隧道层; 并在隧道层上形成电荷陷阱层，屏蔽层和控制栅极电极层。

公开(公告)号：US07824992B2

公开(公告)日：2010-11-02

申请号：US12345785

申请日：2008-12-30

申请人： Moon Sig Joo ,  Heung Jae Cho ,  Yong Soo Kim ,  Won Joon Choi

发明人： Moon Sig Joo ,  Heung Jae Cho ,  Yong Soo Kim ,  Won Joon Choi

IPC分类号： H01L21/4763

CPC分类号： H01L21/28273 ,  H01L21/3145 ,  H01L21/31645 ,  H01L21/76224 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7881

摘要： A method of fabricating a non-volatile memory device includes: forming a tunnel insulation layer pattern and a floating gate electrode layer pattern over a semiconductor substrate; forming an isolation trench by etching an exposed portion of the semiconductor substrate so that the isolation trench is aligned with the tunnel insulation layer pattern and the floating gate electrode layer pattern; forming an isolation layer by filling the isolation trench with a filling insulation layer; forming a hafnium-rich hafnium silicon oxide layer over the isolation layer and the floating gate electrode layer pattern; forming a hafnium-rich hafnium silicon oxynitride layer by carrying out a first nitridation on the hafnium-rich hafnium silicon oxide layer; forming a silicon-rich hafnium silicon oxide layer over the hafnium-rich hafnium silicon oxynitride layer; forming a silicon-rich hafnium silicon oxynitride layer by carrying out a second nitridation on the silicon-rich hafnium silicon oxide layer; and forming a control gate electrode layer over the silicon-rich hafnium silicon oxynitride layer.

摘要翻译： 制造非易失性存储器件的方法包括：在半导体衬底上形成隧道绝缘层图案和浮栅电极层图案; 通过蚀刻半导体衬底的暴露部分形成隔离沟槽，使得隔离沟槽与隧道绝缘层图案和浮栅电极层图案对准; 通过用填充绝缘层填充隔离沟槽来形成隔离层; 在隔离层和浮栅电极层图案上形成富铪铪氧化硅层; 通过在富铪铪氧化硅层上进行第一次氮化，形成富铪铪硅氮化物层; 在富铪铪硅氮化物层上形成富硅铪氧化硅层; 通过在富硅铪氧化硅层上进行第二次氮化，形成富硅铪硅氮氧化物层; 以及在所述富硅铪硅氮氧化物层上形成控制栅电极层。

公开(公告)号：US08105909B2

公开(公告)日：2012-01-31

申请号：US12894021

申请日：2010-09-29

申请人： Moon Sig Joo ,  Heung Jae Cho ,  Yong Soo Kim ,  Won Joon Choi

发明人： Moon Sig Joo ,  Heung Jae Cho ,  Yong Soo Kim ,  Won Joon Choi

IPC分类号： H01L21/4763

CPC分类号： H01L21/28273 ,  H01L21/3145 ,  H01L21/31645 ,  H01L21/76224 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7881

摘要： A method of fabricating a non-volatile memory device includes: forming a tunnel insulation layer pattern and a floating gate electrode layer pattern over a semiconductor substrate; forming an isolation trench by etching an exposed portion of the semiconductor substrate so that the isolation trench is aligned with the tunnel insulation layer pattern and the floating gate electrode layer pattern; forming an isolation layer by filling the isolation trench with a filling insulation layer; forming a hafnium-rich hafnium silicon oxide layer over the isolation layer and the floating gate electrode layer pattern; forming a hafnium-rich hafnium silicon oxynitride layer by carrying out a first nitridation on the hafnium-rich hafnium silicon oxide layer; forming a silicon-rich hafnium silicon oxide layer over the hafnium-rich hafnium silicon oxynitride layer; forming a silicon-rich hafnium silicon oxynitride layer by carrying out a second nitridation on the silicon-rich hafnium silicon oxide layer; and forming a control gate electrode layer over the silicon-rich hafnium silicon oxynitride layer.

摘要翻译： 制造非易失性存储器件的方法包括：在半导体衬底上形成隧道绝缘层图案和浮栅电极层图案; 通过蚀刻半导体衬底的暴露部分形成隔离沟槽，使得隔离沟槽与隧道绝缘层图案和浮栅电极层图案对准; 通过用填充绝缘层填充隔离沟槽来形成隔离层; 在隔离层和浮栅电极层图案上形成富铪铪氧化硅层; 通过在富铪铪氧化硅层上进行第一次氮化，形成富铪铪硅氮化物层; 在富铪铪硅氮化物层上形成富硅铪氧化硅层; 通过在富硅铪氧化硅层上进行第二次氮化，形成富硅铪硅氮氧化物层; 以及在所述富硅铪硅氮氧化物层上形成控制栅电极层。

公开(公告)号：US20110014759A1

公开(公告)日：2011-01-20

申请号：US12894021

申请日：2010-09-29

申请人： Moon Sig Joo ,  Heung Jae Cho ,  Yong Soo Kim ,  Won Joon Choi

发明人： Moon Sig Joo ,  Heung Jae Cho ,  Yong Soo Kim ,  Won Joon Choi

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  H01L21/3145 ,  H01L21/31645 ,  H01L21/76224 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7881

摘要： A method of fabricating a non-volatile memory device includes: forming a tunnel insulation layer pattern and a floating gate electrode layer pattern over a semiconductor substrate; forming an isolation trench by etching an exposed portion of the semiconductor substrate so that the isolation trench is aligned with the tunnel insulation layer pattern and the floating gate electrode layer pattern; forming an isolation layer by filling the isolation trench with a filling insulation layer; forming a hafnium-rich hafnium silicon oxide layer over the isolation layer and the floating gate electrode layer pattern; forming a hafnium-rich hafnium silicon oxynitride layer by carrying out a first nitridation on the hafnium-rich hafnium silicon oxide layer; forming a silicon-rich hafnium silicon oxide layer over the hafnium-rich hafnium silicon oxynitride layer; forming a silicon-rich hafnium silicon oxynitride layer by carrying out a second nitridation on the silicon-rich hafnium silicon oxide layer; and forming a control gate electrode layer over the silicon-rich hafnium silicon oxynitride layer.

摘要翻译： 制造非易失性存储器件的方法包括：在半导体衬底上形成隧道绝缘层图案和浮栅电极层图案; 通过蚀刻半导体衬底的暴露部分形成隔离沟槽，使得隔离沟槽与隧道绝缘层图案和浮栅电极层图案对准; 通过用填充绝缘层填充隔离沟槽来形成隔离层; 在隔离层和浮栅电极层图案上形成富铪铪氧化硅层; 通过在富铪铪氧化硅层上进行第一次氮化，形成富铪铪硅氮化物层; 在富铪铪硅氮化物层上形成富硅铪氧化硅层; 通过在富硅铪氧化硅层上进行第二次氮化，形成富硅铪硅氮氧化物层; 以及在所述富硅铪硅氮氧化物层上形成控制栅电极层。

公开(公告)号：US20090253242A1

公开(公告)日：2009-10-08

申请号：US12345785

申请日：2008-12-30

申请人： Moon Sig Joo ,  Heung Jae Cho ,  Yong Soo Kim ,  Won Joon Choi

发明人： Moon Sig Joo ,  Heung Jae Cho ,  Yong Soo Kim ,  Won Joon Choi

IPC分类号： H01L21/762 ,  H01L21/4763

CPC分类号： H01L21/28273 ,  H01L21/3145 ,  H01L21/31645 ,  H01L21/76224 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7881

摘要： A method of fabricating a non-volatile memory device includes: forming a tunnel insulation layer pattern and a floating gate electrode layer pattern over a semiconductor substrate; forming an isolation trench by etching an exposed portion of the semiconductor substrate so that the isolation trench is aligned with the tunnel insulation layer pattern and the floating gate electrode layer pattern; forming an isolation layer by filling the isolation trench with a filling insulation layer; forming a hafnium-rich hafnium silicon oxide layer over the isolation layer and the floating gate electrode layer pattern; forming a hafnium-rich hafnium silicon oxynitride layer by carrying out a first nitridation on the hafnium-rich hafnium silicon oxide layer; forming a silicon-rich hafnium silicon oxide layer over the hafnium-rich hafnium silicon oxynitride layer; forming a silicon-rich hafnium silicon oxynitride layer by carrying out a second nitridation on the silicon-rich hafnium silicon oxide layer; and forming a control gate electrode layer over the silicon-rich hafnium silicon oxynitride layer.

摘要翻译： 制造非易失性存储器件的方法包括：在半导体衬底上形成隧道绝缘层图案和浮栅电极层图案; 通过蚀刻半导体衬底的暴露部分形成隔离沟槽，使得隔离沟槽与隧道绝缘层图案和浮栅电极层图案对准; 通过用填充绝缘层填充隔离沟槽来形成隔离层; 在隔离层和浮栅电极层图案上形成富铪铪氧化硅层; 通过在富铪铪氧化硅层上进行第一次氮化，形成富铪铪硅氮化物层; 在富铪铪硅氮化物层上形成富硅铪氧化硅层; 通过在富硅铪氧化硅层上进行第二次氮化，形成富硅铪硅氮氧化物层; 以及在所述富硅铪硅氮氧化物层上形成控制栅电极层。

公开(公告)号：US08878319B2

公开(公告)日：2014-11-04

申请号：US13336524

申请日：2011-12-23

申请人： Won Joon Choi

发明人： Won Joon Choi

IPC分类号： H01L29/82 ,  H01L43/02 ,  H01L43/12 ,  H01L43/08

CPC分类号： H01L43/02 ,  H01L43/08 ,  H01L43/12

摘要： A magnetic tunnel junction device includes a first electrode having a curved top surface, a magnetic tunnel junction layer formed along the top surface of the first electrode, and a second electrode formed on the magnetic tunnel junction layer.

摘要翻译： 磁性隧道结装置包括具有弯曲顶表面的第一电极，沿着第一电极的顶表面形成的磁性隧道结层，以及形成在磁性隧道结层上的第二电极。

公开(公告)号：US20120028084A1

公开(公告)日：2012-02-02

申请号：US13143237

申请日：2010-01-06

申请人： Youngsun Park ,  SooRyoung Kim ,  Seunghyun Bang ,  Won Joon Choi

发明人： Youngsun Park ,  SooRyoung Kim ,  Seunghyun Bang ,  Won Joon Choi

IPC分类号： H01M10/48 ,  G01K13/00 ,  H01M2/00 ,  H01M2/10 ,  H01M2/02

CPC分类号： H01M2/34 ,  H01M2/105 ,  H01M2/348 ,  H01M10/486 ,  H01M2200/00 ,  H01M2200/10

摘要： Disclosed herein is a spacer used in a battery pack having a plurality of battery cells mounted in a pack case, wherein the spacer is configured to have a top shape corresponding to the inner shape of the pack case in vertical section and a bottom shape corresponding to the outer circumferential shape of the battery cells in vertical section so that the spacer can be mounted in a space defined between the battery cells and the pack case, grooves, in which electrical connection members are mounted, are formed at the top of the spacer, and the spacer includes at least one temperature detection member mounting part including a horizontal opening open in one direction or in opposite directions and a vertical opening communicating with the horizontal opening so that a temperature detection member is inserted from one side of the spacer and mounted in a space defined between the battery cells. In the spacer, the temperature detection member is inserted into the horizontal opening from one side of the spacer so that the temperature detection member can be fixed between the battery cells and the spacer, and therefore, a process of bonding the temperature detection member is omitted. Also, the electrical connection members for electrical connection between the battery cells and between the battery cells and a protection circuit member are mounted in the grooves so that the electrical connection members are fixed in an insulated state, thereby preventing the occurrence of a short circuit due to vibration or impact and simplifying an assembly process.

摘要翻译： 这里公开了一种用于具有安装在包装盒中的多个电池单元的电池组中的间隔件，其中间隔件构造成具有与垂直部分中的包装盒的内部形状对应的顶部形状，并且底部形状对应于 电池单元的外周形状为垂直截面，使得间隔件可以安装在电池单元和电池壳体之间的空间中，其中安装有电连接构件的槽形成在间隔件的顶部， 并且所述间隔件包括至少一个温度检测构件安装部分，所述温度检测构件安装部分包括沿一个方向或相反方向开口的水平开口和与所述水平开口连通的垂直开口，使得温度检测构件从所述间隔件的一侧插入并安装在 在电池单元之间限定的空间。 在间隔件中，温度检测部件从间隔件的一侧插入到水平开口中，使得温度检测部件能够固定在电池单元和间隔件之间，因此省略了温度检测部件的接合处理 。 此外，用于电池单元之间和电池单元之间的电连接的电连接构件和保护电路构件安装在凹槽中，使得电连接构件被固定在绝缘状态，从而防止发生短路 振动或冲击，简化装配过程。

公开(公告)号：US20110076546A1

公开(公告)日：2011-03-31

申请号：US12920720

申请日：2009-03-07

申请人： Won Joon Choi ,  Youngsun Park ,  John E. Namgoong ,  SooRyoung Kim ,  Myung Hwan Kim

发明人： Won Joon Choi ,  Youngsun Park ,  John E. Namgoong ,  SooRyoung Kim ,  Myung Hwan Kim

IPC分类号： H01M2/24

CPC分类号： H01M2/206 ,  H01M2/1077 ,  H01M2/347 ,  H01M6/46 ,  H01M10/0413 ,  H01M10/0472

摘要： Disclosed herein is a middle- or large-sized battery module having a structure in which two or more plate-shaped secondary battery cells (‘battery cells’) are arranged in a lateral direction thereof, wherein the battery cells have electrode terminals arranged in the same direction, plate-shaped electrode terminal connecting members to electrically connect the battery cells to one another are electrically connected to oriented surfaces of the electrode terminals of the battery cells, each of the electrode terminal connecting members is provided at a top and/or bottom thereof with a coupling structure to interconnect electrode terminal connecting members, and at least one end of an insulating joint member coupled in the coupling structure is supported by a module case.

摘要翻译： 这里公开了一种中型或大型电池模块，其具有两个以上的板状二次电池单体（“电池单元”）沿其横向布置的结构，其中，电池单元具有布置在 相同的方向，将电池单元彼此电连接的板状电极端子连接构件电连接到电池单元的电极端子的取向表面，每个电极端子连接构件设置在顶部和/或底部 其具有用于互连电极端子连接构件的耦合结构，并且耦合在耦合结构中的绝缘接合构件的至少一端由模块壳体支撑。

公开(公告)号：US10090503B2

公开(公告)日：2018-10-02

申请号：US13122004

申请日：2009-10-13

申请人： Won Joon Choi ,  Youngsun Park ,  SooRyoung Kim ,  Ho Yeong Yang ,  Seunghyun Bang ,  Kwang woo Nam

发明人： Won Joon Choi ,  Youngsun Park ,  SooRyoung Kim ,  Ho Yeong Yang ,  Seunghyun Bang ,  Kwang woo Nam

IPC分类号： H01M10/42 ,  H02G5/00 ,  H01R43/02 ,  H01M2/20 ,  H01M2/34 ,  H01M10/052 ,  H01M2/10

摘要： Disclosed herein is an electrode terminal connecting member to connect two or more battery cells in series and/or in parallel to each other so as to manufacture a battery cell core pack, wherein the electrode terminal connecting member includes a plate body having a size sufficient to connect electrode terminals of the battery cells arranged in at least 2×2 matrix to each other, and the electrode terminals of the battery cells are directly coupled to the plate body in a state in which the plate body is not bent.